10
FN6412.1
April 10, 2007
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up
when the dynamic protection is selected. This can be solved
by initiating any power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a predetermined interval. When in static mode, the OLF bit
goes HIGH when the current clamp limit is reached and
returns LOW at the end of initial power-on soft-start. In the
Static mode the output current through the linears is limited to
a 990mA typ.
When a 19.3V line is connected onto a VOUT1 or 2 that has
been set to 13.3V the linear will then enter a back current
limited state. When a back current of greater than 140mA
typical is sensed at the lower FET of the linear for a period
greater that 2ms the output is disabled for a period of 50ms
and the BCF bit is set. If the 19.3V remains connected, the
output will cycle through the ON = 2ms/OFF = 50ms. The
output will return to the setpoint when the fault is removed.
BCF bit is set high during the 50ms OFF period.
Thermal Protection
This IC is protected against overheating. When the junction
temperature exceeds +150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the
SR is set HIGH. When the junction is cooled down to +130°C
(typical), normal operation is resumed and the OTF bit is
reset LOW. If a part is repeatedly driven to the overtemp
shutdown temperature the chip is latched off after the fourth
occurrence and the I
2
C OTF bit is latched high and FLT_bar
low. This OTF counter and FLT_bar can be reset and the
chip restarted by either a power down/up and reload the I
2
C
or power can be left on and the reset accomplished by
toggling the I
2
C bit EN low then back high.
External Output Voltage Selection
When the I
2
C bit VSPEN is set high the output voltage can
be selected by the I
2
C bus. Additionally, the package offers
the pin SELVTOP for independent 13 thru 19V output
voltage selection., when the VSPEN bit is set low. A
summary of the voltage control is given in Table 1. For
further details refer to the individual registers SR1 and SR3
I
2
C Bus Interface for ISL6423B
(Refer to Philips I
2
C Specification, Rev. 2.1)
Data transmission from main microprocessor to the ISL6423B
and vice versa takes place through the two wire I
2
C bus
interface, consisting of the two lines SDA and SCL. Both SDA
and SCL are bidirectional lines, connected to a positive supply
voltage via a pull up resistor. (Pull up resistors to positive supply
voltage must be externally connected). When the bus is free,
both lines are HIGH. The output stages of ISL6423B will have
an open drain/open collector in order to perform the wired-AND
function. Data on the I
2
C bus can be transferred up to 100Kbps
in the standard-mode or up to 400Kbps in the fast-mode. The
level of logic “0” and logic “1” is dependent of associated value
of V
DD
as per electrical specification table. One clock pulse is
generated for each data bit transferred.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 4.
START and STOP Conditions
As shown in Figure 5, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
TABLE 1.
VSPEN VTOP VBOT SELVTOP VOUT
0 x 0 0 13.3V
0 x 1 0 14.3V
0 0 x 1 18.3V
0 1 x 1 19.3V
1 0 0 x 13.3V
1 0 1 x 14.3V
1 1 0 x 18.3V
1 1 1 x 19.3V
SDA
SCL
DATA LINE
STABLE
DATA VALID
CHANGE
OF DATA
ALLOWED
FIGURE 4. DATA VALIDITY
SDA
SCL
START
CONDITION
FIGURE 5. START AND STOP WAVEFORMS
STOP
CONDITION
SP
