10
ICS950810
0472F—01/12/04
1. The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
A
CK
Dummy Command Code
A
CK
Dummy Byte Count
ACK
Byte 0
A
CK
Byte 1
A
CK
Byte 2
ACK
Byte 3
A
CK
Byte 4
A
CK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Write:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
A
CK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Read:
11
ICS950810
0472F—01/12/04
I2C Tables
Pin # Name 0 1 PWD
Bit 7 - Spread Enabled Spread Spectrum Control RW OFF ON 0
Bit 6 - CPU_T(2:0)
Power down mode output
level
0= CPU driven in power
down
1= undriven
RW HIGH LOW 0
Bit 5 35 3V66_1/VCH_CLK VCH/66.66 Select RW 66.66 48.00 0
Bit 4 53 CPU_STOP#* Reflects value of pin R Stop Active X
Bit 3 34 PCI_STOP#*
Reflects value of pin at
power up. Also can be set.
R/RW Stop Active 1
Bit 2 40 FS2 Frequency Selection RW - - X
Bit 1 55 FS1 Frequency Selection RW - - X
Bit 0 54 FS0 Frequency Selection RW - - X
Control Function
Affected Pin
BYTE
0T
y
pe
Bit Control
Pin # Name 0 1 PWD
Bit 7 43 MULTSEL0* Reflects value of pin R - - x
Bit 6 - CPU_T(2:0)
CPU_Stop mode output level
0= CPU driven when stopped
1 = undriven
RW HIGH LOW 0
Bit 5 45, 44
CPUCLKT2
CPUCLKC2
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
Freerun 0
Bit 4 49, 48
CPUCLKT1
CPUCLKC1
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
Freerun 0
Bit 3 52, 51
CPUCLKT0
CPUCLKC0
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
Freerun 0
Bit 2 45, 44
CPUCLKT2
CPUCLKC2
Output control RW Disable Enable 1
Bit 1 49, 48
CPUCLKT1
CPUCLKC1
Output control RW Disable Enable 1
Bit 0 52, 51
CPUCLKT2
CPUCLKC2
Output control RW Disable Enable 1
BYTE
1
Control Function
Affected Pin
Type
Bit Control
12
ICS950810
0472F—01/12/04
Pin # Name 0 1 PWD
Bit 7 - - (Reserved) - - - 0
Bit 6 18 PCICLK6 Output control RW Disable Enable 1
Bit 5 17 PCICLK5 Output control RW Disable Enable 1
Bit 4 16 PCICLK4 Output control RW Disable Enable 1
Bit 3 13 PCICLK3 Output control RW Disable Enable 1
Bit 2 12 PCICLK2 Output control RW Disable Enable 1
Bit 1 11 PCICLK1 Output control RW Disable Enable 1
Bit 0 10 PCICLK0 Output control RW Disable Enable 1
BYTE
2
Control Function
Affected Pin
Type
Bit Control
Pin # Name 0 1 PWD
Bit 7 38 48MHz_DOT Output control RW Disable Enable 1
Bit 6 39 48MHz_USB Output control RW Disable Enable 1
Bit 5 7 PCICLK_F2
Allow control of output with
assertion of PCI_STOP#.
RW Freerun
Not
Freerun
0
Bit 4 6 PCICLK_F1
Allow control of output with
assertion of PCI_STOP#.
RW Freerun
Not
Freerun
0
Bit 3 5 PCICLK_F0
Allow control of output with
assertion of PCI_STOP#.
RW Freerun
Not
Freerun
0
Bit 2 7 PCICLK_F2 Output control RW Disable Enable 1
Bit 1 6 PCICLK_F1 Output control RW Disable Enable 1
Bit 0 5 PCICLK_F0 Output control RW Disable Enable 1
Control Function
BYTE
3
Affected Pin Bit Control
Type
Pin # Name 0 1 PWD
Bit 7 - - (Reserved) RW Disable Enable 0
Bit 6 - - (Reserved) RW Disable Enable 0
Bit 5 33 3V66_0 Output control RW Disable Enable 1
Bit 4 35 3V66_1/VCH_CLK Output control RW Disable Enable 1
Bit 3 24 3V66_5 Output control RW Disable Enable 1
Bit 2 23 3V66_4 Output control RW Disable Enable 1
Bit 1 22 3V66_3 Output control RW Disable Enable 1
Bit 0 21 3V66_2 Output control RW Disable Enable 1
Type
Bit Control
Control Function
Affected PinBYTE
4

950810CGLF

Mfr. #:
Manufacturer:
Description:
Clock Generators & Support Products PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet