NXP Semiconductors
TEA19362T
GreenChip SMPS primary side control IC with fixed frequency operation
TEA19362T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 9 August 2016
10 / 34
When the system stops switching, the VCCH and VCCL pins are not supplied via the
auxiliary winding anymore. Depending on the protection triggered, V
VCCL
is either
regulated to the V
startup
level via the HV pin or dropped down until the UVLO protection
triggered (see Table 4).
8.6.1 OverPower Protection (OPP)
The overpower protection function is used to realize a maximum output power which is
nearly constant over the full input mains.
For applications intended to operate fully in DCM mode, a constant overpower protection
level can be set by using the flat portion of the OPP curve (see Figure 6). On the other
hand, applications designed to operate in QR mode at maximum power require the OPP
level to be compensated for mains. They can be set to use the variable part of the OPP
curve.
The resistors connected to the AUX pin set the I
AUX
. They determine which part of the
OPP curve is used by the application.
The overpower compensation circuit measures the input voltage via the AUX pin. The
circuit outputs an overpower reference voltage that depends on this input voltage. If
the measured voltage at the ISENSE pin exceeds the overpower reference voltage
(V
opp(ISENSE)
), the DRIVER output is pulled low (the primary stroke is cut short). The
overpower timer starts. In this way, the system limits the power to the maximum rated
value on a cycle-by-cycle base. If the overpower situation persists continuously for
192 ms, an overpower time-out is triggered. Figure 6 shows the overpower protection
curve.
region optimized
for DCM operation
region optimized
for QR operation
Figure 6. Overpower protection curve
During system start-up, the maximum time-out period is lowered to 38.4 ms. When
the output voltage is within its regulation level, the maximum time-out period returns
to 192 ms, limiting the output power to a minimum at a shorted output. Shortening the
overpower timer ensures that the input power of the system is limited to < 5 W at a
shorted output.
If the load requires more power than allowed by the OPP limit, the output voltage drops
because of the limited output power. As a result, the V
CC
voltage also drops and UVLO
can be triggered. To retain the same response in an overpower situation (whether UVLO
is triggered or not), the system enters the overpower protection mode when overpower
and UVLO are detected. The system entering the protection mode does not depend on
the value of the OP counter.