M2041
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
The M2041 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator PLL. It is designed
for clock protection, frequency translation and jitter
attenuation in optical networking systems supporting
2.5-10Gb data rates. It features dual differential inputs
with two modes of input selection: manual and
automatic upon clock failure. The clock multiplication
ratios and output divider ratio are pin selectable.
External loop components allow the tailoring of PLL
loop response.
FEATURES
• Integrated SAW (surface acoustic wave) delay line;
output frequencies of 125 to 700 MHz;
*
outputs
VCSO frequency or 1/4; pin-configurable dividers
• Loss of Lock (LOL) indicator output
• Narrow Bandwidth control input (NBW pin);
Initialization (
INIT) input overrides NBW at power-up
• Dual reference clock inputs support LVDS, LVPECL,
LVCMOS, LVTTL
• AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure;
Hitless Switching (HS) options with or without
Phase Build-out (PBO) enable SONET (GR-253)
/SDH (G.813) MTIE and TDEV compliance
• Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
• Dual differential LVPECL outputs
• Low phase jitter of < 0.5ps rms, typical
(12kHz to 20MHz or 50kHz to 80MHz)
• Single 3.3V power supply
• Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
Example I/O Clock Frequency Combinations
Using
M2041-11-622.0800
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
19.44 32
622.08
or
155.52
77.76 8
155.52 4
622.08 1
M2041
(Top View)
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
FIN_SEL1
GND
AUTO
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
P_SEL
INIT
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
FIN_SEL0
MR_SEL
REF_ACK
LOL
NBW
VCC
DNC
DNC
DNC
nOP_IN
OP_OUT
VC
nVC
nOP_OUT
OP_IN
GND
GND
GND
19
20
21
22
23
24
25
26
27
Loop Filter
PLL
Phase
Detector
MR_SEL
FIN_SEL1:0
R Div
(1 or 8)
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
1
Mfin Divider
LUT
Mfin Divider
(1, 4, 8, or 32)
M Divider
(1 or 8)
P_SEL
NBW
M / R Divider
LUT
DIF_REF1
nDIF_REF1
Auto
Ref Sel
0
1
LOL
Phase
Detector
REF_ACK
AUTO
INIT
LOL
M2041
2
VCSO
FOUT0
nFOUT0
P Divider
(1 or 4)
FOUT1
nFOUT1
M2041 VCSO Based Clock PLL with AutoSwitch
