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4.9 Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector or chip erase operation
and then program or read data from a different sector within the memory. After the Erase Sus-
pend command is given, the device requires a maximum time of 15 µs to suspend the erase
operation. After the erase operation has been suspended, the system can then read data or
program data to any other sector within the device. An address is not required during the
Erase Suspend command. During a sector erase suspend, another sector cannot be erased.
To resume the sector erase operation, the system must write the Erase Resume command.
The Erase Resume command is a one-bus cycle command. The device also supports an
erase suspend during a complete chip erase. While the chip erase is suspended, the user can
read from any sector within the memory that is protected. The command sequence for a chip
erase suspend and a sector erase suspend are the same.
4.10 Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command
is given, the device requires a maximum of 20 µs to suspend the programming operation. After
the programming operation has been suspended, the system can then read data from any
other word that is not contained in the sector in which the programming operation was sus-
pended. An address is not required during the program suspend operation. To resume the
programming operation, the system must write the Program Resume command. The program
suspend and resume are one-bus cycle commands. The command sequence for the erase
suspend and program suspend are the same, and the command sequence for the erase
resume and program resume are the same.
4.11 Product Identification
The product identification mode identifies the device and manufacturer as Atmel
®
. It is
accessed using a software operation.
For details, see “Operating Modes” on page 16 or “Software Product Identification Entry/Exit”
sections on page 23.
4.12 128-bit Protection Register
The AT49SV163D(T) contains a 128-bit register that can be used for security purposes in sys-
tem design. The protection register is divided into two 64-bit blocks. The two blocks are
designated as block A and block B. The data in block A is non-changeable and is programmed
at the factory with a unique number. The data in block B is programmed by the user and can
be locked out such that data in the block cannot be reprogrammed. To program block B in the
protection register, the four-bus cycle Program Protection Register command must be used as
shown in the “Command Definition Table” on page 12. To lock out block B, the four-bus cycle
Lock Protection Register command must be used as shown in the “Command Definition
Table” . Data bit D1 must be zero during the fourth bus cycle. All other data bits during the
fourth bus cycle are don’t cares. To determine whether block B is locked out, the Product ID
Entry command is given followed by a read operation from address 80H. If data bit D1 is zero,
block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the “Protec-
tion Register Addressing Table” on page 13 for the address locations in the protection register.
To read the protection register, the Product ID Entry command is given followed by a normal
read operation from an address within the protection register. After determining whether block
B is protected or not, or reading the protection register, the Product ID Exit command must be
given prior to performing any other operation.
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4.13 RDY/BUSY
An open-drain READY/BUSY output pin provides another method of detecting the end of a
program or erase operation. RDY/BUSY
is actively pulled low during the internal program and
erase cycles and is released at the completion of the cycle. The open-drain connection allows
for OR-tying of several devices to the same RDY/BUSY
line. Please see “Status Bit Table” on
page 11 for more details.
4.14 Common Flash Interface (CFI)
CFI is a published, standardized data structure that may be read from a flash device. CFI
allows system software to query the installed device to determine the configurations, various
electrical and timing parameters, and functions supported by the device. CFI is used to allow
the system to learn how to interface to the flash device most optimally. The two primary bene-
fits of using CFI are ease of upgrading and second source availability. The command to enter
the CFI Query mode is a one-bus cycle command which requires writing data 98h to address
55h. The CFI Query command can be written when the device is ready to read data or can
also be written when the part is in the product ID mode. Once in the CFI Query mode, the sys-
tem can read CFI data at the addresses given in “Common Flash Interface Definition Table”
on page 24. To exit the CFI Query mode, the product ID exit command must be given.
4.15 Hardware Data Protection
The Hardware Data Protection feature protects against inadvertent programs to the
AT49SV163D(T) in the following ways: (a) V
CC
sense: if V
CC
is below 1.65V (typical), the pro-
gram function is inhibited. (b) V
CC
power-on delay: once V
CC
has reached the V
CC
sense level,
the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE
low, CE high or WE high inhibits program cycles. (d) Program inhibit:
V
PP
is less than V
ILPP.
4.16 Input Levels
While operating with a 1.65V to 1.95V power supply, the address inputs and control inputs
(OE
, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of
the device. The I/O lines can only be driven from 0 to V
CC
+ 0.6V.
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AT49SV163D(T)
Figure 4-1. Data Polling Algorithm
(Configuration Register = 00)
Notes: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1” because
I/O7 may change simultaneously with I/O5.
START
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
I/O3, I/O5 = 1?
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
NO
NO
NO
YES
YES
YES
Program/Erase
Operation
Successful,
Device in
Read Mode
Figure 4-2. Data Polling Algorithm
(Configuration Register = 01)
Notes: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1” because
I/O7 may change simultaneously with I/O5.
START
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
I/O3, I/O5 = 1?
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
NO
NO
NO
YES
YES
YES
Program/Erase
Operation
Successful,
Write Product ID
Exit Command

AT49SV163DT-80TU

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash Parallel Flash 1.8V 80NS, GR
Lifecycle:
New from this manufacturer.
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