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NLAST4051DTR2G

P1-P3P4-P6P7-P9P10-P12
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 5
1 Publication Order Number:
NLAST4051/D
NLAST4051
Analog Multiplexer/
Demultiplexer
TTL Compatible, Single−Pole, 8−Position
Plus Common Off
The NLAST4051 is an improved version of the MC14051 and
MC74HC4051 fabricated in sub−micron Silicon Gate CMOS technology
for lower R
DS(on)
resistance and improved linearity with low current.
This device may be operated either with a single supply or dual supply up
to ±3 V to pass a 6 V
PP
signal without coupling capacitors.
When operating in single supply mode, it is only necessary to tie
V
EE
, pin 7 to ground. For dual supply operation, V
EE
is tied to a
negative voltage, not to exceed maximum ratings. Translation is
provided in the device, the Address and Inhibit are standard TTL level
compatible. For CMOS compatibility see NLAS4051. Pin for pin
compatible with all industry standard versions of ‘4051.’
Features
• Improved R
DS(on)
Specifications
• Pin for Pin Replacement for MAX4051 and MAX4051A
− One Half the Resistance Operating at 5.0 V
• Single or Dual Supply Operation
− Single 3.0 − 5.0 V Operation, or Dual ±3 V Operation
− With V
CC
of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
− No Translators Needed
− Address and Inhibit Logic are Over−Voltage Tolerant and May Be
− Driven Up +6 V Regardless of V
CC
• Address and Inhibit Pins Standard TTL Compatible
− Greatly Improved Noise Margin Over MAX4051 and MAX4051A
− True TTL Compatibility V
IL
= 0.8 V, V
IH
= 2.0 V
• Improved Linearity Over Standard HC4051 Devices
• Space Saving TSSOP Package
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Figure 1. Pin Connection
(Top View)
1516 14 13 12 11 10
21 34567
V
CC
9
8
NO
2
NO
4
NO
0
NO
6
ADD
C
ADD
B
ADD
A
NO
1
NO
3
COM NO
7
NO
5
Inhibit V
EE
GND
www.onsemi.com
MARKING
DIAGRAM
TSSOP−16
DT SUFFIX
CASE 948F
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
AST
4051
ALYWG
G
(Note: Microdot may be in either location)
1
1
16
Figure 2. Logic Diagram
NO
4
NO
7
Inhibit
NO
6
NO
3
ADD
A
LOGIC
ADD
B
ADD
C
NO
5
NO
2
NO
1
NO
0
COM
NLAST4051
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2
TRUTH TABLE
Inhibit
Address
ON SWITCHES*
C B A
1 X
don’t care
X
don’t care
X
don’t care
All switches open
0 0 0 0 COM−NO
0
0 0 0 1 COM−NO
1
0 0 1 0 COM−NO
2
0 0 1 1 COM−NO
3
0 1 0 0 COM−NO
4
0 1 0 1 COM−NO
5
0 1 1 0 COM−NO
6
0 1 1 1 COM−NO
7
*NO and COM pins are identical and interchangeable. Either may be considered
an input or output; signals pass equally well in either direction.
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
EE
Negative DC Supply Voltage (Referenced to GND) −7.0 to )0.5 V
V
CC
Positive DC Supply Voltage (Note 1) (Referenced to GND)
(Referenced to V
EE
)
−0.5 to )7.0
−0.5 to )7.0
V
V
IS
Analog Input Voltage V
EE
−0.5 to V
CC
)0.5 V
V
IN
Digital Input Voltage (Referenced to GND) −0.5 to 7.0 V
I DC Current, Into or Out of Any Pin $50 mA
T
STG
Storage Temperature Range −65 to )150 °C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
T
J
Junction Temperature under Bias )150 °C
JA
Thermal Resistance 164 °C/W
P
D
Power Dissipation in Still Air 450 mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
u1000
V
I
LATCHUP
Latchup Performance Above V
CC
and Below GND at 125°C (Note 5) $300 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The absolute value of V
CC
$|V
EE
| ≤ 7.0.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
NLAST4051
www.onsemi.com
3
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
EE
Negative DC Supply Voltage (Referenced to GND) −5.5 GND V
V
CC
Positive DC Supply Voltage (Referenced to GND)
(Referenced to V
EE
)
2.5
2.5
5.5
6.6
V
V
IS
Analog Input Voltage V
EE
V
CC
V
V
IN
Digital Input Voltage (Note 6) (Referenced to GND) 0 5.5 V
T
A
Operating Temperature Range, All Package Types −55 125 °C
t
r
, t
f
Input Rise/Fall Time V
CC
= 3.0 V $ 0.3 V
(Channel Select or Enable Inputs) V
CC
= 5.0 V $ 0.5 V
0
0
100
20
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Unused digital inputs may not be left open. All digital inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Symbol
Parameter Condition
V
CC
V
Guaranteed Limit
Unit
−55 to 25°C v85°C v125°C
V
IH
Minimum High−Level Input Voltage,
Address or Inhibit Inputs
3.0
4.5
5.5
1.6
2.0
2.0
1.6
2.0
2.0
1.6
2.0
2.0
V
V
IL
Maximum Low−Level Input Voltage,
Address or Inhibit Inputs
3.0
4.5
5.5
0.5
0.8
0.8
0.5
0.8
0.8
0.5
0.8
0.8
V
I
IN
Maximum Input Leakage Current,
Address or Inhibit Inputs
V
IN
= 6.0 or GND 0 V to 6.0 V $0.1 $1.0 $1.0
A
I
CC
Maximum Quiescent Supply
Current (per Package)
Address or Inhibit and
V
IS
= V
CC
or GND
6.0 4.0 40 80
A
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
DC ELECTRICAL CHARACTERISTICS − Analog Section
Symbol Parameter Test Conditions
V
CC
V
V
EE
V
Guaranteed Limit
Unit
−55 to 25°C v85°C v125°C
R
ON
Maximum “ON” Resistance V
IN
= V
IL
or V
IH
V
IS
= (V
EE
to V
CC
)
|I
S
| = 10 mA
(Figures 4 thru 9)
3.0
4.5
3.0
0
0
−3.0
86
37
26
108
46
33
120
55
37
R
ON
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Pack-
age
V
IN
= V
IL
or V
IH,
V
IS
= 2.0 V
V
IS
= 3.0 V
|I
S
| = 10 mA, V
IS
= 2.0 V
3.0
4.5
3.0
0
0
−3.0
15
13
10
20
18
15
20
18
15
Rflat
(ON)
ON Resistance Flatness V
COM
= 1, 2, 3.5 V
V
COM
= 2, 0, 2 V
4.5
3.0
3.0
4
2
4
2
5
3
I
NC(OFF)
I
NO(OFF)
Maximum Off−Channel
Leakage Current
Switch Off
V
IN
= V
IL
or V
IH
V
IO
= V
CC
−1.0 V or V
EE
+1.0 V
(Figure 17)
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
I
COM(ON)
Maximum On−Channel
Leakage Current,
Channel−to−Channel
Switch On
V
IO
= V
CC
−1.0 V or V
EE
+1.0 V
(Figure 17)
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
P1-P3P4-P6P7-P9P10-P12

NLAST4051DTR2G

Mfr. #:
Buy NLAST4051DTR2G
Manufacturer:
ON Semiconductor
Description:
Multiplexer Switch ICs SP8T Mux/Demux TTL Compat -55 to 125
Lifecycle:
New from this manufacturer.
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