NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
10 / 45
Table 7. Bump allocation table of the NHS3100W8 package
Bump Symbol Bump Symbol
1 PIO0_0/WAKEUP 7 TP1
2 TP0 8 VSS
3 LA 9 VDDBAT
4 LB 10 PIO0_6
5 PIO0_11/CT32B_M1/SWDIO 11 TP2
6 PIO0_10/CT32B_M0/SWCLK 12 TP3
Table 8. Bump description of the NHS3100W8 package
Bump Symbol Type Description
Supply
9 VDDBAT supply positive supply voltage
8 VSS supply ground
GPIO
[1]
PIO0_0 I/O GPIO1
WAKEUP I Deep power-down mode wake-up pin
[2]
10 PIO0_6 I/O GPIO
PIO0_10 I/O GPIO
CT32B_M0 O 32-bit timer match output 0
6
SWCLK I ARM SWD clock
PIO0_11 I/O GPIO
CT32B_M1 O 32-bit timer match output 1
5
SWDIO I/O ARM SWD I/O
Radio
3 LA A NFC antenna/coil terminal A
4 LB A NFC antenna/coil terminal B
Test pins
2 TP0 - test pin - do not connect
7 TP1 - test pin - do not connect, or connect to ground
11 TP2 - test pin - do not connect
12 TP3 - test pin - do not connect
[1] The GPIO port is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 balls
depends on the function selected through the IOCONFIG register block.
[2] If external wake-up is enabled on this ball, it must be pulled HIGH before entering Deep power-down mode and pulled
LOW for a minimum of 100 μs to exit Deep power-down mode.
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
11 / 45
8 Functional description
8.1 ARM Cortex-M0+ core
Refer to the Cortex-M0+ Devices Technical Reference Manual (Ref. 1) for a detailed
description of the ARM Cortex-M0+ processor.
The NHS3100 ARM Cortex-M0+ core has the following configuration:
System options
Nested Vectored Interrupt Controller (NVIC)
Fast (single-cycle) multiplier
System tick timer
Support for wake-up interrupt controller
Vector table remapping register
Reset of all registers
Debug options
Serial Wire Debug (SWD) with two watchpoint comparators and four breakpoint
comparators
Halting debug is supported
8.2 Memory map
Figure 5 shows the memory and peripheral address space of the NHS3100.
The only AHB peripheral device on the NHS3100 is the GPIO module. The APB
peripheral area is 512 kB in size. Each peripheral is allocated 16 kB of space.
All peripheral register addresses are 32-bit word aligned. Byte and halfword addressing is
not possible. All reading and writing are done per full word.
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
12 / 45
Figure 5. NHS3100 memory map
8.3 System configuration
The system configuration APB block controls oscillators, start logic, and clock generation
of the NHS3100. Also included in this block is a register for remapping the interrupt
vector table.
8.3.1 Clock generation
The NHS3100 Clock Generator Unit (CGU) includes two independent RC oscillators.
These oscillators are the System Free-Running Oscillator (SFRO) and the Timer Free-
Running Oscillator (TFRO).

NHS3100UK/A1Z

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC RFID READER 13.56MHZ 25WLCSP
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New from this manufacturer.
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