OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

HEF40373BT,652

P1-P3P4-P6P7-P9P10-P12P13-P15
Nexperia
HEF40373B
Octal transparent latch with 3-state outputs
Symbol Parameter Conditions Extrapolation formula Min Typ Max Unit
EO to On; see Figure 11.
V
DD
= 5 V - 65 130 ns
V
DD
= 10 V - 30 60 ns
t
PHZ
HIGH to OFF-state
propagation delay
V
DD
= 15 V - 25 50 ns
EO to On; see Figure 11.
V
DD
= 5 V - 75 150 ns
V
DD
= 10 V - 40 80 ns
t
PLZ
LOW to OFF-state
propagation delay
V
DD
= 15 V - 30 60 ns
On; see Figure 9 and
Figure 10.
V
DD
= 5 V - 40 80 ns
V
DD
= 10 V - 20 40 ns
t
THL
HIGH to LOW output
transition time
V
DD
= 15 V - 15 30 ns
On; see Figure 9 and
Figure 10.
V
DD
= 5 V - 30 60 ns
V
DD
= 10 V - 20 40 ns
t
TLH
LOW to HIGH output
transition time
V
DD
= 15 V - 15 30 ns
Dn to E; see Figure 12.
V
DD
= 5 V 15 7 - ns
V
DD
= 10 V 10 5 - ns
t
su
set-up time
V
DD
= 15 V 10 5 - ns
Dn to E; see Figure 12.
V
DD
= 5 V 25 15 - ns
V
DD
= 10 V 15 4 - ns
t
h
hold time
V
DD
= 15 V 10 3 - ns
E; LOW; see Figure 13.
V
DD
= 5 V 60 30 - ns
V
DD
= 10 V 30 15 - ns
t
W
pulse width
V
DD
= 15 V 20 10 - ns
[1] The typical values of the propagation delay are calculated from the extrapolation formulas shown (C
L
in pF).
Table 8. Dynamic power dissipation
Symbol Parameter V
DD
Typical formula where:
5 V P
D
= 3325 × f
i
+ Σ(f
o
× C
L
) × V
DD
2
(μW)
10 V P
D
= 14200 × f
i
+ Σ(f
o
× C
L
) × V
DD
2
(μW)
P
D
dynamic power
dissipation
15 V P
D
= 37425 × f
i
+ Σ(f
o
× C
L
) × V
DD
2
(μW)
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
Σ(f
o
× C
L
) = sum of the outputs;
V
DD
= supply voltage in V.
HEF40373B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 4 — 29 June 2018
7 / 15
Nexperia
HEF40373B
Octal transparent latch with 3-state outputs
10.1 Waveforms and test circuit
V
DD
- V
OH
(V)
-2 -1 0
aaa-027602
0
I
OH
(mA)
-100
-25
-50
(2)
-75
V
DD
= 5 V
10 V
15 V
(1)
(1) P-channel MOS transistor conducting.
(2) P-channel MOS transistor and bipolar n-p-n transistor
conducting.
Figure 7. Typical output source current characteristic.
Figure 8. Schematic diagram of output stage.
aaa-028683
output
input
t
PHL
t
THL
t
TLH
t
PLH
V
M
V
M
V
DD
V
SS
V
OH
90 % 90 %
10 %10 %
V
OL
V
M
V
M
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Figure 9. Input to output propagation delays and output transition time.
HEF40373B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 4 — 29 June 2018
8 / 15
Nexperia
HEF40373B
Octal transparent latch with 3-state outputs
C
L
(pF)
10 10
4
10
3
10
2
aaa-027604
10
3
10
2
10
4
t
THL
t
TLH
(ns)
10
V
DD
= 5 V
10 V
15 V
V
DD
= 5 V
10 V
15 V
t
THL
t
TLH
Figure 10. Output transition times as a function of the load capacitance
aaa-028690
outputs off outputs onoutputs on
V
Y
V
X
V
M
V
Y
V
X
V
DD
V
SS
V
DD
V
OL
V
OH
EO input
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
V
SS
t
PZL
t
PLZ
t
PHZ
t
PZH
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Figure 11. 3-state enable and disable times
HEF40373B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 4 — 29 June 2018
9 / 15
P1-P3P4-P6P7-P9P10-P12P13-P15

HEF40373BT,652

Mfr. #:
Buy HEF40373BT,652
Manufacturer:
Nexperia
Description:
Latches OCT TRANSP LATCH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet