6
FN2857.10
August 11, 2015
The hold capacitor terminal (pin 11) remains at virtual ground
potential. Any PC connection to this terminal should be kept
short and “guarded” by the ground plane, since nearby
signal lines or power supply voltages will introduce errors
due to drift current.
Typical Application
Figure 5 shows the HA-5320 connected as a unity gain
noninverting amplifier - its most widely used configuration.
As an input device for a fast successive - approximation A/D
converter, it offers very high throughput rate for a monolithic
IC sample/hold amplifier. Also, the HA-5320’s hold step error
is adjustable to zero using the Offset Adjust potentiometer, to
deliver a 12-bit accurate output from the converter.
The application may call for an external hold capacitor C
EXT
as
shown. As mentioned earlier, 0.1C
EXT
is then recommended at
pin 8 to reduce output noise in the Hold mode.
The HA-5320 output circuit does not include short circuit
protection, and consequently its output impedance remains
low at high frequencies. Thus, the step changes in load
current which occur during an A/D conversion are absorbed
at the S/H output with minimum voltage error. A momentary
short circuit to ground is permissible, but the output is not
designed to tolerate a short of indefinite duration.
Glossary of Terms
Acquisition Time
The time required following a “sample” command, for the
output to reach its final value within 0.1% or 0.01%. This is
the minimum sample time required to obtain a given accuracy,
and includes switch delay time, slewing time and settling time.
Charge Transfer
The small charge transferred to the holding capacitor from
the inter-electrode capacitance of the switch when the unit is
switched to the HOLD mode. Charge transfer is directly
proportional to sample-to-hold offset pedestal error, where:
Charge Transfer (pC) = C
H
(pF) x Hold Step Error (V)
Aperture Time
The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is the interval
between the conditions of 10% open and 90% open.
Hold Step Error
Hold Step Error is the output error due to Charge Transfer (see
above). It may be calculated from the specified parameter,
Charge Transfer, using the following relationship:
See Performance Curves.
Effective Aperture Delay Time (EADT)
The difference between the digital delay time from the Hold
command to the opening of the S/H switch, and the
propagation time from the analog input to the switch.
EADT may be positive, negative or zero. If zero, the S/H
amplifier will output a voltage equal to V
IN
at the instant the
Hold command was received. For negative EADT, the output in
Hold (exclusive of pedestal and droop errors) will correspond to
a value of V
IN
that occurred before the Hold command.
Aperture Uncertainty
The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay Uncertainty,
Aperture Time Jitter, etc.) sets a limit on the accuracy with
which a waveform can be reconstructed from sample data.
Drift Current
The net leakage current from the hold capacitor during the
hold mode. Drift current can be calculated from the droop
rate using the formula:
Hold Step (V)
Charge Transfer (pC)
Hold Capacitance (pF)
------------------------------------------------------------
=
I
D
(pA) C
H
pF
V
t
--------
(V/s)=
NOTE: Pin Numbers Refer to
DIP Package Only.
+
-
3459
10k
OFFSET
ADJUST
15mV
1
2
HA-5320
H
S
S
/H CONTROL
V
IN
14
-15V +15V
+
-
11
100pF
7
0.1C
EXT
SYSTEM POWER
GROUND
SYSTEM SIGNAL
GROUND
68
13
5
9
ANALOG
COMMON
R/C
INPUT
HI-574A
DIGITAL
OUTPUT
CONVERT
C
EXT
13
FIGURE 5. TYPICAL HA-5320 CONNECTIONS; NONINVERTING UNITY GAIN MODE
HA-5320
