Philips Semiconductors Product data
PCK210
Low voltage dual 1:5 differential
ECL/PECL clock driver
2
2004 Apr 23
FEATURES
• 85 ps part-to-part skew typical
• 20 ps output-to-output skew typical
• Differential design
• V
BB
output
• Voltage and temperature compensated outputs
• Low voltage V
EE
range of –2.25 V to –3.8 V
• 75 kΩ input pull-down resistors
• Form, fit, and function compatible with MC100EP210
DESCRIPTION
The PCK210 is a low skew 1-to-5 dual differential driver, designed
with clock distribution in mind. The input signals can be either
differential or single-ended if the V
BB
output is used. The signal is
fanned out to 5 identical differential outputs.
The PCK210 is specifically designed, modeled and produced with
low skew as the key goal. Optimal design and layout serve to
minimize gate-to-gate skew within a device, and empirical modeling
is used to determine process control limits that ensure consistent
t
PD
distributions from lot to lot. The net result is a dependable,
guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary that
both sides of the differential output are terminated into 50 Ω, even if
only one side is being used. In most applications, all ten differential
pairs will be used, and therefore terminated. In the case where fewer
than ten pairs are used, it is necessary to terminate at least the
output pairs on the same package side as the pair(s) being used on
that side, in order to maintain minimum skew. Failure to do this will
result in small degradations of propagation delay (on the order of
10–20 ps) of the output(s) being used, which, while not being
catastrophic to most designs, will mean a loss of skew margin.
The PCK210, as with most other ECL devices, can be operated
from a positive V
CC
supply in PECL mode. This allows the PCK210
to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Designers can take advantage of the PCK210’s
performance to distribute low skew clocks across the backplane or
the board. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power
supplies.
The PCK210 may be driven single-endedly utilizing the V
BB
bias
output with the CLKA
or CLKB input. If a single-ended signal is to be
used, the V
BB
pin should be connected to the CLKA or CLKB input
and bypassed to ground via a 0.01 µF capacitor. The V
BB
output
can only source/sink 0.3 mA, therefore, it should be used as a
switching reference for the PCK210 only. Part-to-part skew
specifications are not guaranteed when driving the PCK210
single-endedly.
PINNING
Pin configurations
V
BB
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
QA3
QA3
QA4
QA4
QB0
QB0
QB1
QB1
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
PCK210BD
SW00909
V
QB4
QB4
QB3
QB3
QB2
QB2
n.c.
CLKA
CLKA
CLKB
CLKB
QA0
QA0
QA1
QA1
QA2
QA2
V
EE
V
CC
CCO
V
CCO
V
CCO
V
CCO
Figure 1. LQFP32 pin configuration
PCK210BS
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
CC
V
CCO
n.c.
CLKA
CLKA
CLKB
CLKB
V
BB
V
EE
QB4
QB4
QB3
QB3
QB2
QB2
V
CCO
QA3
QA3
QA4
QA4
QB0
QB0
QB1
QB1
V
CCO
V
CCO
QA0
QA0
QA1
QA1
QA2
QA2
SW02237
Figure 2. HVQFN32 pin configuration
ORDERING INFORMATION
Package
Temperature
u
Name Description Version
range
PCK210BD LQFP32 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm SOT358-1 –40 °C to +85 °C
PCK210BS HVQFN32
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 × 5 × 0.85 mm
SOT617-1 –40 °C to +85 °C
