LTC2751
13
2751fa
operaTion
Table 1 shows the functions of the LTC2751.
Table 1. Write, Update and Read Functions
READ D/S WR UPD SPAN I/O DATA I/O
0 0 0 0 - Write to Input Register
0 0 0 1 - Write/Update
(Transparent)
0 0 1 0 - -
0 0 1 1 Update DAC Register Update DAC Register
0 1 0 0 Write to Input Register -
0 1 0 1 Write/Update
(Transparent)
-
0 1 1 0 - -
0 1 1 1 Update DAC register Update DAC Register
1 0 X 0 - Read Input Register
1 0 X 1 - Read DAC Register
1 1 X 0 Read Input Register -
1 1 X 1 Read DAC Register -
X = Don’t Care
Manual Span Configuration
Multiple output ranges are not needed in some applications.
To configure the LTC2751 for single-span operation, tie the
MSPAN pin to V
DD
and the D/S pin to GND. The desired
output range is then specified by the span I/O pins (S0, S1
and S2) as usual, but the pins are programmed by tying
directly to GND or V
DD
(see Figure 1 and Table 2). In this
configuration, the part will initialize to the chosen output
range at power-up, with V
OUT
= 0V.
When configured for manual span operation, span pin
readback is disabled.
Write and Update Operations
The data input register is loaded directly from a 16-bit
microprocessor bus by holding the D/S
pin low and then
pulsing
the WR pin low. The second register (DAC regis-
ter) is loaded by pulsing the UPD pin high, which copies
the data held in the input register into the DAC register.
Note that updates always include both data and span; but
the DAC register values will not change unless the input
register values have been changed by writing.
Loading the span input register is accomplished in a similar
manner, by holding the D/S pin high and then bringing
the WR pin low. The span and data register structures
are the same except for the number of parallel bits—the
span registers have three bits, while the data registers
have 12, 14, or 16 bits.
To make both registers transparent for flowthrough mode,
tie WR low and UPD high. However, this defeats the de-
glitcher operation and output glitch impulse may increase.
The deglitcher is activated on the rising edge of the UPD pin.
The interface also allows the use of the input and DAC
registers in a master-slave, or edge-triggered, configura-
tion. This mode of operation occurs when WR and UPD
are tied together and driven by a single clock signal. The
data bits are
loaded into the input register on the falling
edge of the clock and then loaded into the DAC register
on the rising edge.
The separation of data and span for write and read opera-
tions makes it possible to control both data and span on
one 16-bit wide data bus by allowing span pins S2 to S0
to share bus lines with the data LSBs (D2 to D0). Since
no write or read operation includes both span and data,
there cannot be a conflict.
The asynchronous clear pin resets the LTC2751 to 0V
(zero-, half- or quarter-scale code) in any output range.
CLR resets both the input and DAC data registers, while
leaving the span registers undisturbed.
These devices also have a power-on reset. If configured
for SoftSpan operation, the part initializes to zero scale in
the 0V to 5V output range. If configured for single-span
operation, the part initializes to the zero-volt code in the
chosen output range.
Figure 1. Configuring the LTC2751 for
Single-Span Operation (±10V Range)
LTC2751-16
MSPAN
S2
S1
S0
D/S
V
DD
2751 F01
WR UPD READ
DATA I/O
16
DD
