4
IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Truth Table I: Chip Enable
(1,2)
Truth Table II: Non-Contention Read/Write Control
NOTES:
1. A
0L – A16L ≠ A0R – A16R.
2. Refer to Chip Enable Truth Table.
Truth Table III: Semaphore Read/Write Control
(1)
NOTES:
1. There are eight semaphore flags written to via I/O
0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
NOTES:
1. Chip Enable references are shown above with the actual CE
0 and CE1 levels, CE is a reference only.
2. 'H' = V
IH and 'L' = VIL.
3. CMOS standby requires 'X' to be either
< 0.2V or > VCC - 0.2V.
CE CE
0
CE
1
Mode
L
V
IL
V
IH
Port Selected (TTL Active)
<
0.2V >V
CC
-0.2V Port Selected (CMOS Active)
H
V
IH
X Port Deselected (TTL Inactive)
XV
IL
Port Deselected (TTL Inactive)
>
V
CC
-0.2V X Port Deselected (CMOS Inactive)
X<
0.2V Port Deselected (CMOS Inactive)
4839 tbl 06
Inputs
(1 )
Outputs
Mode
CE
(2 )
R/W
OE SEM
I/O
0-7
H X X H High-Z Deselected: Power-Down
LLXHDATA
IN
Write to memory
LHLHDATA
OUT
Read memory
X X H X High-Z Outputs Disabled
4839 drw 07
Inputs Outputs
Mode
CE
(2)
R/W
OE SEM
I/O
0-7
HHLLDATA
OUT
Read Semaphore Flag Data Out
H
↑
XLDATA
IN
Write I/O
0
into Semaphore Flag
LXXL
______
Not Allowed
4839 tbl 08