Rev.1.60 Jan 27, 2006 page 5 of 26
REJ03B0034-0160
R8C/11 Group
1. Overview
Package: PLQP0032GB-A (32P6U-A)
Figure 1.3 Pin Assignments (Top View)
PIN CONFIGURATION (top view)
1 2 3 4 5 6 7 8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
9
2
8
2
7
2
6
2
5
2
4 2
3 2
2 2
1 2
0 1
9 1
8 1
7
3
2
3
1
3
0
R8C/11 Group
X
I
N
/
P
4
6
V
S
S
R
E
S
E
T
V
C
C
C
N
V
S
S
P
1
7
/
I
N
T
1
/
C
N
T
R
0
P1
6
/CLK
0
P1
5
/RxD
0
P1
4
/TxD
0
P
3
7
/
T
x
D
1
0
/
R
x
D
1
P
3
0
/
C
N
T
R
0
/
C
M
P
1
0
P
3
3
/
I
N
T
3
/
P
3
1
/
T
Z
O
U
T
/
C
M
P
1
1
P
3
2
/
I
N
T
2
/
C
N
T
R
1
/
C
M
P
1
2
I
V
C
C
A
V
S
S
A
V
C
C
/
V
R
E
F
P0
3
/AN
4
P0
2
/AN
5
P0
1
/AN
6
P
0
0
/
A
N
7
/T
x
D
1
1
P
0
6
/
A
N
1
P0
5
/AN
2
P
0
4
/
A
N
3
P4
5
/INT
0
P1
0
/KI
0
/AN
8
/CMP0
0
P1
1
/KI
1
/AN
9
/CMP0
1
P1
2
/KI
2
/AN
10
/CMP0
2
P1
3
/KI
3
/AN
11
P
0
7
/
A
N
0
MODE
T
C
I
N
N
O
T
E
S
:
1
.
P
4
7
f
u
n
c
t
i
o
n
s
o
n
l
y
a
s
a
n
i
n
p
u
t
p
o
r
t
.
2.
W
h
e
n
u
s
i
n
g
O
n
-
c
h
i
p
d
e
b
u
g
g
e
r
,
d
o
n
o
t
u
s
e
p
i
n
s
P
0
0
/
A
N
7
/
T
x
D
1
1
a
n
d
P
3
7
/
T
x
D
1
0
/
R
x
D
1
.
3
.
D
o
n
o
t
c
o
n
n
e
c
t
I
V
c
c
t
o
V
c
c
.
X
O
U
T
/
P
4
7
(
1
)
1.5 Pin Assignments
Figure 1.3 shows the pin configuration (top view).
Rev.1.60 Jan 27, 2006 page 6 of 26
REJ03B0034-0160
R8C/11 Group
1. Overview
Signal name Pin name I/O type
Power supply Vcc, I
input Vss
IVcc IVcc O
Analog power AVcc, AVss I
supply input
Reset input
___________
RESET I
CNVss CNVss I
MODE MODE I
Main clock input XIN I
Main clock output XOUT O
_____
INT interrupt input
_______ _______
INT0 to INT3 I
Key input interrupt
_____ _____
KI0 to KI3 I
Timer X CNTR0 I/O
____________
CNTR0 O
Timer Y CNTR1 I/O
Timer Z TZOUT O
Timer C TCIN I
CMP00 to CMP02,
O
CMP10 to CMP12
Serial interface CLK0 I/O
RxD0, RxD1 I
TxD0, TxD10,O
TxD11
Reference voltage VREF I
input
A/D converter AN0 to AN11 I
I/O port P00 to P07, I/O
P10 to P17,
P30 to P33, P37,
P45
Input port P46, P47 I
Function
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the
Vss pin.
This pin is to stabilize internal power supply.
Connect this pin to Vss via a capacitor (0.1 µF).
Do not connect to Vcc.
Power supply input pins for A/D converter. Connect the
AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a
capacitor between pins AVcc and AVss.
Input L on this pin resets the MCU.
Connect this pin to Vss via a resistor.
Connect this pin to Vcc via a resistor.
These pins are provided for the main clock generat-
ing circuit I/O. Connect a ceramic resonator or a crys-
tal oscillator between the XIN and XOUT pins. To use
an externally derived clock, input it to the XIN pin and
leave the XOUT pin open.
______
INT interrupt input pins.
Key input interrupt pins.
Timer X I/O pin
Timer X output pin
Timer Y I/O pin
Timer Z output pin
Timer C input pin
Timer C output pins
Transfer clock I/O pin.
Serial data input pins.
Serial data output pins.
Reference voltage input pin for A/D converter. Con-
nect the VREF pin to Vcc.
Analog input pins for A/D converter
These are 8-bit CMOS I/O ports. Each port has an I/O
select direction register, allowing each pin in that port
to be directed for input or output individually.
Any port set to input can select whether to use a pull-
up resistor or not by program.
P10 to P17 also function as LED drive ports.
Port for input-only
1.6 Pin Description
Table 1.3 shows the pin description
Table 1.3 Pin description
R8C/11 Group 2. Central Processing Unit (CPU)
Rev.1.60 Jan 27, 2006 page 7 of 26
REJ03B0034-0160
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. Two sets of register banks are provided.
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0
can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.
The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit
data register (R2R0). The same applies to R3R1 as R2R0.
D
a
t
a
r
e
g
i
s
t
e
r
s
(
1
)
A
d
d
r
e
s
s
r
e
g
i
s
t
e
r
s
(
1
)
F
r
a
m
e
b
a
s
e
r
e
g
i
s
t
e
r
s
(
1
)
P
r
o
g
r
a
m
c
o
u
n
t
e
r
I
n
t
e
r
r
u
p
t
t
a
b
l
e
r
e
g
i
s
t
e
r
U
s
e
r
s
t
a
c
k
p
o
i
n
t
e
r
Interrupt stack pointer
Static base register
Flag register
N
O
T
E
S
:
1
.
A
r
e
g
i
s
t
e
r
b
a
n
k
c
o
m
p
r
i
s
e
s
t
h
e
s
e
r
e
g
i
s
t
e
r
s
.
T
w
o
s
e
t
s
o
f
r
e
g
i
s
t
e
r
b
a
n
k
s
a
r
e
p
r
o
v
i
d
e
d
R0H (high-order of R0)
b
1
5
b
8
b7 b
0
R
3
I
N
T
B
H
U
S
P
ISP
SB
CDZSBOIU
I
P
L
R0L (low-order of R0)
R1H (high-order of R1)
R1L (low-order of R1)
R
2
b
3
1
R3
R2
A1
A0
F
B
b
1
9
I
N
T
B
L
b
1
5
b
0
PC
b19
b
0
b
1
5
b
0
F
L
G
b15 b0
b
1
5
b
0
b7 b
8
Reserved bit
Carry flag
D
e
b
u
g
f
l
a
g
Z
e
r
o
f
l
a
g
Sign flag
Register bank select flag
O
v
e
r
f
l
o
w
f
l
a
g
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
f
l
a
g
S
t
a
c
k
p
o
i
n
t
e
r
s
e
l
e
c
t
f
l
a
g
R
e
s
e
r
v
e
d
b
i
t
Processor interrupt priority level
T
h
e
4
-
h
i
g
h
o
r
d
e
r
b
i
t
s
o
f
I
N
T
B
a
r
e
I
N
T
B
H
a
n
d
t
h
e
1
6
-
l
o
w
b
i
t
s
o
f
I
N
T
B
a
r
e
I
N
T
B
L
.
Figure 2.1 CPU Register

R5F21112DFP#U0

Mfr. #:
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU MCU 3/5V 8K I-Temp Pb-Free 32-LQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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