RT8075
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DS8075-04 April 2011 www.richtek.com
Applications Information
The basic RT8075 application circuit is shown in Typical
Application Circuit. External component selection is
determined by the maximum load current and begins with
the selection of the inductor value and operating frequency
followed by C
IN
and C
OUT
.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔI
L
increases with higher V
IN
and decreases
with higher inductance.
Having a lower ripple current reduces the ESR losses in
the output capacitors and the output voltage ripple. Highest
efficiency operation is achieved at low frequency with small
ripple current. This, however, requires a large inductor.
A reasonable starting point for selecting the ripple current
is ΔI
L
= 0.4(I
MAX
). The largest ripple current occurs at the
highest V
IN
. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation :
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or mollypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates hard, which means that
inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage ripple.
Do not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy materials
are small and don't radiate energy but generally cost more
than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and
any radiated field/EMI requirements.
C
IN
and C
OUT
Selection
The input capacitance, C
IN
, is needed to filter the
trapezoidal current at the source of the top MOSFET. To
prevent large ripple voltage, a low ESR input capacitor
sized for the maximum RMS current should be used. RMS
current is given by :
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple current
ratings from capacitor manufacturers are often based on
only 2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a higher
temperature than required. Several capacitors may also
be paralleled to meet size or height requirements in the
design.
The selection of C
OUT
is determined by the Effective Series
Resistance (ESR) that is required to minimize voltage
ripple and load step transients, as well as the amount of
bulk capacitance that is necessary to ensure that the
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple, ΔV
OUT
, is determined by :
⎡⎤
⎡⎤
Δ−
⎢⎥
⎢⎥
⎣⎦
⎣⎦
OUT OUT
L
IN
VV
I = x 1
f x L V
⎡⎤⎡⎤
⎢⎥⎢⎥
Δ
⎢⎥⎢⎥
⎣⎦⎣⎦
OUT OUT
L(MAX) IN(MAX)
VV
L = x 1
f x I V
OUT
IN
RMS OUT(MAX)
IN OUT
V
V
I = I 1
VV
⎡⎤
Δ≤Δ
⎢⎥
⎣⎦
OUT L
OUT
1
V I ESR +
8fC
RT8075
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DS8075-04 April 2011www.richtek.com
The output ripple is highest at maximum input voltage
since ΔI
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capacitors
have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, V
IN
. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at V
IN
large enough to damage the
part.
Output Voltage Setting
The resistive divider allows the FB pin to sense a fraction
of the output voltage as shown in Figure 1.
Figure 1. Setting Output Voltage
where V
REF
is the internal reference voltage (0.6V typ.)
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used
by the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability problem.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
D(MAX)
= (T
J(MAX)
T
A
) / θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature, T
A
is the ambient temperature and the θ
JA
is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
the RT8075, The maximum junction temperature is 125°C.
The junction to ambient thermal resistance θ
JA
is layout
dependent. For WDFN-10L 3x3 package, the thermal
resistance θ
JA
is 68°C/W on the standard JEDEC 51-7
four layers thermal test board. The maximum power
dissipation at T
A
= 25°C can be calculated by following
formula :
P
D(MAX)
= (125°C 25°C) / (68°C/W) = 1.471W for
WDFN-10L 3x3
For adjustable voltage mode, the output voltage is set by
an external resistive divider according to the following
equation :
RT8075
GND
FB
R1
R2
V
OUT
⎛⎞
+
⎜⎟
⎝⎠
OUT REF
R1
V = V 1
R2
RT8075
9
DS8075-04 April 2011 www.richtek.com
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8075.
` Keep the trace of the main current paths as short and
wide as possible.
` Put the input capacitor as close as possible to the device
pins (VIN1 / VIN2 and GND).
` LX 1 / LX 2 node is with high frequency voltage swing
and should be kept at small area. Keep analog
components away from the LX 1 / LX 2 node to prevent
stray capacitive noise pick-up.
` Place the feedback components as close as possible to
the FB1 / FB2 pins.
` The GND and Exposed Pad must be connected to a
strong ground plane for heat sinking and noise protection.
Figure 2. Derating Curves for RT8075 Package
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
. For RT8075 package, the Figure 2 of
derating curve allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation allowed.
EN1
FB1
LX2
GND
LX1
GND
VIN1
EN2
FB2
VIN2
9
8
7
9
1
2
3
4
5
10
GND
11
L1
C
IN1
C
OUT1
R3
V
OUT2
V
OUT1
R4
R2
V
OUT1
R1
L2
C
IN2
C
OUT2
V
OUT2
C
FF1
C
FF2
GND
Figure 3. PCB Layout Guide
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W)
Four Layers PCB

RT8075ZQW

Mfr. #:
Manufacturer:
Description:
IC REG BUCK ADJ 1A DL 10WDFN
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New from this manufacturer.
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