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UJA1076ATW/3V3,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47
UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 34 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
V
th(RX)dif
differential receiver threshold
voltage
CAN Active mode
V
V2
= 4.5 V to 5.5 V
−30 V < V
CANH
< 30 V
−30 V < V
CANL
< 30 V
0.5 0.7 0.9 V
CAN Lowpower mode
−12 V < V
CANH
< 12 V
−12 V < V
CANL
< 12 V
0.4 0.7 1.15 V
V
hys(RX)dif
differential receiver
hysteresis voltage
CAN Active mode
V
V2
= 4.5 V to 5.5 V
−30 V < V
CANH
< 30 V
−30 V < V
CANL
< 30 V
40 120 400 mV
R
i(cm)
common-mode input
resistance
CAN Active mode; V
V2
= 5 V
V
CANH
= V
CANL
= 5 V
91528kΩ
ΔR
i
input resistance deviation CAN Active mode; V
V2
= 5 V
V
CANH
= V
CANL
=5V
−1- +1 %
R
i(dif)
differential input resistance CAN Active mode; V
V2
= 5.5 V
V
CANH
= V
CANL
= −35 V to +35 V
19 30 52 kΩ
C
i(cm)
common-mode input
capacitance
CAN Active mode; not tested - - 20 pF
C
i(dif)
differential input capacitance CAN Active mode; not tested - - 10 pF
I
LI
input leakage current V
BAT
= 0 V; V
V2
= 0 V
V
CANH
= V
CANL
=5V
−5 - +5 μA
CAN bus common mode stabilization output; pin SPLIT
V
O
output voltage CAN Active mode
V
V2
= 4.5 V to 5.5 V
I
SPLIT
= −500 μA to 500 μA
0.3V
V2
0.5V
V2
0.7V
V2
V
CAN Active mode
V
V2
= 4.5 V to 5.5 V; R
L
≥ 1MΩ
0.45 ×
V
V2
0.5 ×
V
V2
0.55 ×
V
V2
V
I
L
leakage current CAN Lowpower/Off mode or Active
mode with V
V2
< 4.5 V
V
SPLIT
= −30 V to + 30 V
−5- +5 μA
Temperature protection
T
th(act)otp
overtemperature protection
activation threshold
temperature
165 180 200 °C
T
th(rel)otp
overtemperature protection
release threshold
temperature
126 138 150 °C
Table 10. Static characteristics
…continued
T
vj
=
−
40
°
C to +150
°
C; V
BAT
= 4.5 V to 28 V; V
BAT
> V
V1
; V
BAT
> V
V2
; R
(CANH-CANL)
= 45
Ω
to 65
Ω
; all voltages are defined
with respect to ground; positive currents flow in the IC; typical values are given at V
BAT
= 14 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 35 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
10. Dynamic characteristics
Table 11. Dynamic characteristics
T
vj
=
−
40 °C to +150
°
C; V
BAT
= 4.5 V to 28 V; V
BAT
> V
V1
; V
BAT
> V
V2
; R
(CANH-CANL)
= 45
Ω
to 65
Ω
; all voltages are defined
with respect to ground; positive currents flow in the IC; typical values are given at V
BAT
= 14 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Voltage source; pin V1
t
d(uvd)
undervoltage detection delay
time
V
V1
falling; dV
V1
/dt = 0.1 V/μs7-23μs
t
det(CL)L
LOW-level clamping detection
time
V
V1
<0.9V
O(V1)nom
; V1 active
V
WDOFF
= 0 V (WD versions only)
95 - 140 ms
Voltage source; pin V2
t
d(uvd)
undervoltage detection delay
time
V
V2
falling, dV
V2
/dt = 0.1 V/us 7 - 23 μs
Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO
t
cy(clk)
clock cycle time V
V1
= 2.97 V to 5.5 V 320 - - ns
t
SPILEAD
SPI enable lead time V
V1
= 2.97 V to 5.5 V; clock is LOW
when SPI select falls
110 - - ns
t
SPILAG
SPI enable lag time V
V1
= 2.97 V to 5.5 V; clock is LOW
when SPI select rises
140 - - ns
t
clk(H)
clock HIGH time V
V1
= 2.97 V to 5.5 V 160 - - ns
t
clk(L)
clock LOW time V
V1
= 2.97 V to 5.5 V 160 - - ns
t
su(D)
data input set-up time V
V1
= 2.97 V to 5.5 V 0 - - ns
t
h(D)
data input hold time V
V1
= 2.97 V to 5.5 V 80 - - ns
t
v(Q)
data output valid time pin SDO; V
V1
= 2.97 V to 5.5 V
C
L
= 100 pF
--110ns
t
WH(S)
chip select pulse width HIGH V
V1
= 2.97 V to 5.5 V 20 - - ns
Reset output; pin RSTN
t
w(rst)
reset pulse width long; R
pu(RSTN)
> 25 kΩ 20 - 25 ms
short; R
pu(RSTN)
= 900 Ω to 1100 Ω 3.6 - 5 ms
t
det(CL)L
LOW-level clamping detection
time
RSTN driven HIGH internally but pin
RSTN remains LOW; V
WDOFF
=0 V
(WD versions only)
95 - 140 ms
t
fltr
filter time 7 - 18 μs
Watchdog off input; pin WDOFF
t
fltr
filter time 0.9 - 2.3 ms
Wake input; pin WAKE1, WAKE2
t
wake
wake-up time 10 - 40 μs
t
d(po)
power-on delay time 113 - 278 μs
CAN transceiver timing; pins CANH, CANL, TXDC and RXDC
t
d(TXDCH-RXDCH)
delay time from TXDC HIGH
to RXDC HIGH
50 % V
TXDC
to 50 % V
RXDC
V
V2
= 4.5 V to 5.5 V
R
(CANH-CANL)
= 60 Ω
C
(CANH-CANL)
= 100 pF; C
RXDC
= 15 pF
f
TXDC
= 250 kHz
60 - 235 ns
UJA1076A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 36 of 47
NXP Semiconductors
UJA1076A
High-speed CAN core system basis chip
t
d(TXDCL-RXDCL)
delay time from TXDC LOW
to RXDC LOW
50 % V
TXDC
to 50 % V
RXDC
V
V2
= 4.5 V to 5.5 V
R
(CANH-CANL)
= 60 Ω
C
(CANH-CANL)
= 100 pF
C
RXDC
=15 pF; f
TXDC
= 250 kHz
60 - 235 ns
t
d(TXDC-busdom)
delay time from TXDC to bus
dominant
V
V2
= 4.5 V to 5. 5 V
R
(CANH-CANL)
= 60 Ω
C
(CANH-CANL)
= 100 pF
-70- ns
t
d(TXDC-busrec)
delay time from TXDC to bus
recessive
V
V2
= 4.5 V to 5.5 V
R
(CANH-CANL)
= 60 Ω
C
(CANH-CANL)
= 100 pF
-90- ns
t
d(busdom-RXDC)
delay time from bus dominant
to RXDC
V
V2
= 4.5 V to 5.5 V
R
(CANH-CANL)
= 60 Ω
C
(CANH-CANL)
= 100 pF
C
RXDC
= 15 pF
-75- ns
t
d(busrec-RXDC)
delay time from bus recessive
to RXDC
V
V2
= 4.5 V to 5.5 V
R
(CANH-CANL)
= 60 Ω
C
(CANH-CANL)
= 100 pF
C
RXDC
= 15 pF
-95- ns
t
wake(busdom)min
minimum bus dominant
wake-up time
first pulse (after first recessive) for
wake-up on pins CANH and CANL
Sleep mode
0.5 - 3 μs
second pulse for wake-up on pins
CANH and CANL
0.5 - 3 μs
t
wake(busrec)min
minimum bus recessive
wake-up time
first pulse for wake-up on pins CANH
and CANL; Sleep mode
0.5 - 3 μs
second pulse (after first dominant) for
wake-up on pins CANH and CANL
0.5 - 3 μs
t
to(wake)
wake-up time-out time between wake-up and confirm
messages; Sleep mode
0.4 - 1.2 ms
t
to(dom)TXDC
TXDC dominant time-out time CAN online; V
V2
= 4.5 V to 5.5 V
V
TXDC
= 0 V
1.8 - 4.5 ms
Wake bias output; pin WBIAS
t
WBIASL
WBIAS LOW time 227 - 278 μs
t
cy
cycle time WBC = 1 58.1 - 71.2 ms
WBC = 0 14.5 - 17.8 ms
Watchdog
t
trig(wd)1
watchdog trigger time 1 Normal mode
watchdog Window mode only
[1]
0.45 ×
NWP
[2]
- 0.555 ×
NWP
[2]
ms
t
trig(wd)2
watchdog trigger time 2 Normal, Standby and Sleep modes
watchdog Window mode only
[3]
0.9 ×
NWP
[2]
-1.11 ×
NWP
[2]
ms
Table 11. Dynamic characteristics
…continued
T
vj
=
−
40 °C to +150
°
C; V
BAT
= 4.5 V to 28 V; V
BAT
> V
V1
; V
BAT
> V
V2
; R
(CANH-CANL)
= 45
Ω
to 65
Ω
; all voltages are defined
with respect to ground; positive currents flow in the IC; typical values are given at V
BAT
= 14 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47

UJA1076ATW/3V3,118

Mfr. #:
Buy UJA1076ATW/3V3,118
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC Hi Spd CAN Transcvr 4.5V-28V
Lifecycle:
New from this manufacturer.
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