DESCRIPTION
Demonstration circuit 1143 is a 20 W att Isolated Fly-
back Converter w ith Synchronous Rectification and
Primary-Side Regulation featuring the LT3825.
This circuit w as designed to demonstrate the high lev-
els of performance, efficiency, and small solution size
attainable using this part in a flyback pow er supply. It
operates at 250kHz and produces a regulated 3.3V, 6A
output from an input voltage range of 36 to 72V: suit-
able for telecom and other applications. It has a foot-
print area that is 1.0 inch square. Synchronous rectifi-
cation helps to attain efficiency exceeding 88%. Isola-
tion voltage is 1500VDC.
Design files for this circuit board are available. Call
the LTC factory.
, LTC, LTM , LT, Burst M ode, OPTI-LOO P, Over-The-Top and PolyPhase are registered
trademarks of Linear Technology Corporation. Adaptive Pow er, C-Load, DirectSense, Easy
Drive, FilterCAD, Hot Sw ap, LinearView , µM odule, M icropow er Sw itcherCAD, M ultimode
Dimming, No Latency , No Latency Delta-Sigma, No R
SENSE
, Operational Filter, PanelProtect,
Pow erPath, Pow erSOT, SmartStart, SoftSpan, Stage Shedding, Sw itcherCAD, ThinSOT,
UltraFast and VLDO are trademarks of Linear Technology Corporation. Other product names
may be trademarks of the companies that manufacture the products.
P ER F O R M A N C E S U M M A R Y
Specifications are at TA = 25°C
SYM BO L PARAM ETER CONDITIONS M IN TYP M AX UNITS
V
IN
Input Supply Range
36 72 V
V
OUT
Output Voltage 3.3 V
I
OUT
Output Current Range V
IN
= 36 –72V
0 6 A
F
SW
Sw itching (Clock) Frequency
250 kHz
V
OUT P-P
Output Ripple V
IN
= 48V, I
OUT
= 6A (20M Hz BW ) 20 mV
P–P
I
REG
Output Regulation Line and Load (36-72V, 0-6A)
±1.2 %
P
OUT
/P
IN
Efficiency (see Figure 2) V
IN
=48V, I
OUT
= 6A
88.5 %
O P ER A T IN G P R IN C IP L ES
The LT3825 Synchronous Flyback PW M Controller is
used on the primary and drives a secondary-side
M OSFET through a pulse transformer to provide a
synchronous rectified output.
W hen an input voltage is applied, an undervoltage cir-
cuit keeps the LT3825 in its quiescent state w hile a
resistor charges Cvcc (C10) to 15V. The controller is
then enabled, and start-up commences. The primary
circuit operates from the charge stored in Cvcc until
the housekeeping w inding of T1 starts to support Vcc.
W hen a heavy overload or short-circuit prevents T1
supporting Vcc, the converter operates in ‘burp-
mode’, cutting off w hen Vcc declines to 10V, main-
taining low pow er dissipation in the circuit. The
LT3825 provides a synchronous rectifier gate drive
signal w hich is passed to the secondary through T2
and subsequently buffered.
Regulation is attained by observing the voltage on the
housekeeping w inding of T1 during the Flyback time,
and Pulse W idth M odulating (PW M ) the Primary Gate
drive (PG) and Synchronous G ate drive (SG). The
Q U IC K S TA R T G U IDE
L T 3 8 2 5
Iso la te d F ly b a c k C o n v e rte r w ith
S y n c h ro n o u s R e c tific a tio n
