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MAX3784UTE+

P1-P3P4-P6P7-P7
MAX3784/MAX3784A
5Gbps PCB Equalizer
4 _______________________________________________________________________________________
Typical Operating Characteristics
(V
CC
= +3.3V, measurements done at 5Gbps, 800mV
P-P
board input with 100-bit pattern from Note 2 of the
EC Table
,T
A
= +25°C,
unless otherwise noted.)
55mV/
div
EQUALIZER INPUT EYE DIAGRAM
BEFORE EQUALIZATION AT 5Gbps
(40in, FR-4, 6-mil STRIPLINE)
MAX3784/4A toc01
32ps/div
80mV/
div
EQUALIZER OUTPUT EYE DIAGRAM
AFTER EQUALIZATION AT 5Gbps
(40in, FR-4, 6-mil STRIPLINE, MAX3784)
MAX3784/4A toc02
35ps/div
80mV/
div
EQUALIZER OUTPUT EYE DIAGRAM
AFTER EQUALIZATION AT 5Gbps
(40in, FR-4, 6-mil STRIPLINE, MAX3784A)
MAX3784/4A toc03
35ps/div
0
10
5
20
15
25
30
05
DIFFERENTIAL RETURN LOSS
MAX3784/4A toc04
FREQUENCY (GHz)
RETURN LOSS (dB)
2134
0
30
20
10
40
50
60
70
80
90
100
02010 30 40 50 60
DETERMINISTIC JITTER
vs. LINE LENGTH
MAX3784/4A toc05
LINE LENGTH (in)
(FR-4 6-mil STRIPLINE)
DETERMINISTIC JITTER (ps)
1.25GHz
2.5GHz
5GHz
0
30
20
10
40
50
60
70
80
90
100
200 600400 800 1000 1200
DETERMINISTIC JITTER vs. AMPLITUDE
(20in FR-4 STRIPLINE)
MAX3784/4A toc06
INPUT AMPLITUDE (mV
P-P
)
(FIGURE 1, POINT A)
DETERMINISTIC JITTER (ps)
1.25GHz
2.5GHz
5GHz
0
30
20
10
40
50
60
70
80
90
100
200 600400 800 1000 1200
DETERMINISTIC JITTER vs. AMPLITUDE
(40in FR-4 STRIPLINE)
MAX3784/4A toc07
INPUT AMPLITUDE (mV
P-P
)
(FIGURE 1, POINT A)
DETERMINISTIC JITTER (ps)
1.25GHz
2.5GHz
5GHz
0
100
300
200
400
500
LATENCY vs. TEMPERATURE
MAX3784/4A toc08
TEMPERATURE (°C)
LATENCY (ps)
05025 75 100
0
10
20
30
40
50
60
70
80
0255075
SUPPLY CURRENT vs. TEMPERATURE
MAX3784/4A toc09
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
I
CC
MAX3784
I
CC
MAX3784A
I
SHUTDOWN
Detailed Description
General Theory of Operation
The MAX3784/MAX3784A adaptive equalizers extend
the reach of transmission lines in high-frequency back-
plane interconnect applications. They can be used for
4.25Gbps Fibre Channel, 4x 1.25Gbps Ethernet (5Gbps)
and other NRZ, 8b10b or short (≤ 20 bits) CID data
types. Internally, the MAX3784/MAX3784A are com-
prised of an equalizer control loop and limiting output
driver. The equalizer block reduces intersymbol interfer-
ence (ISI), compensating for frequency-dependent
media-induced loss. The equalization control detects the
spectral contents of the input signal and provides a con-
trol voltage to the equalizer core, adapting it to different
media. The equalizer operation is optimized for short-run,
DC-balanced transmission codes.
Standby Mode
Standby saves power when the equalizer is not in use.
The EN logic input must be set high or open for normal
operation. Logic low at EN forces the equalizer into the
standby state.
CML Input and Output Buffers
The input and output buffers are implemented using cur-
rent-mode logic (CML). Equivalent circuits are shown in
Figures 3 and 4. For details on interfacing with CML,
refer to Maxim Application Note HFAN-01.0:
Introduction
to LVDS, PECL, and CML
. The common-mode voltage
of the input and output is above +2.5V. AC-coupling
capacitors are required when interfacing this part with
devices terminated in voltages such as +1.8V. Values of
0.10µF or greater are recommended.
MAX3784/MAX3784A
5Gbps PCB Equalizer
_______________________________________________________________________________________________________ 5
Pin Description
PIN NAME FUNCTION
1, 7, 12 V
CC
+3.3V Supply Voltage
2 IN+ Positive Input, CML
3 IN- Negative Input, CML
4, 6, 9 GND Supply Ground
5, 8, 14, 15,
16
N.C. No Connection. Leave unconnected.
10 OUT- Negative Output, CML
11 OUT+ Positive Output, CML
13 EN
Enable Equalizer. A logic high or open selects normal operation. A logic low selects low-power
standby mode.
EP
Exposed
Pad
Connect to Ground. The exposed pad must be soldered to the circuit board ground plane for proper
thermal and electrical performance.
IN+
IN-
EN
LIMITER
5Gbps EQUALIZER
OUT+
OUT-
V
CC
EQUALIZER
OFFSET
CANCELLATION
LOWPASS FILTER
50Ω
100Ω
40kΩ
50Ω
V
CC
MAX3784/
MAX3784A
Figure 2. Functional Diagram
MAX3784/MAX3784A
Applications Information
Alternate Data Rates
The MAX3784/MAX3784A is optimized for automatic
operation at 5Gbps. Equalization at other data rates,
such as 1.25Gbps and 2.5Gbps, is possible. See the
Typical Operating Characteristics
for Deterministic Jitter
vs. Line Length and Deterministic Jitter vs. Amplitude
for typical performance at these data rates.
Layout Considerations
Circuit board layout and design can significantly affect
the MAX3784/MAX3784As’ performance. Use good
high-frequency design techniques, including minimiz-
ing ground inductance and connections and using con-
trolled-impedance transmission lines for the
high-frequency data signals. Route signals differentially
to reduce EMI susceptibility and crosstalk. Solder the
exposed pad to supply ground for proper thermal and
electrical operation.
Place power-supply decoupling capacitors as close as
possible to the V
CC
pins.
5Gbps PCB Equalizer
6 _______________________________________________________________________________________
50Ω
50Ω
V
CC
250μA
Figure 3. CML Input Equivalent Circuit
V
CC
50Ω 50Ω
OUT+
OUT-
Figure 4. CML Output Equivalent Circuit
15
16
14
13
6
5
7
IN+
GND
8
V
CC
OUT+
GND
V
CC
12
N.C.
4
12 11 9
N.C.
N.C.
N.C.
V
CC
GND
N.C.
MAX3784
MAX3784A
IN- OUT-
3
10
EN
TQFN
TOP VIEW
* THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND
FOR CORRECT THERMAL AND ELECTRICAL PERFORMANCE.
*EP
+
Pin Configurations (continued)
P1-P3P4-P6P7-P7

MAX3784UTE+

Mfr. #:
Buy MAX3784UTE+
Manufacturer:
Maxim Integrated
Description:
Equalizers 5Gbps PCB Equalizer
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