6.42
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
5
Timing Waveform of Read Cycle No. 1
(1,2,3)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
AC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Range)
DATA
OUT
ADDRESS
3210 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
,
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
t
RC
Read Cycle Time 12
____
15
____
20
____
ns
t
AA
Address Access Time
____
12
____
15
____
20 ns
t
ACS
Chip Select Access Time
____
12
____
15
____
20 ns
t
CLZ
(1)
Chip Select Low to Output in Low-Z 4
____
5
___ _
5
___ _
ns
t
CHZ
(1)
Chip Select High to Output in High-Z
____
6
___ _
6
___ _
8ns
t
OE
Output Enable Low to Output Valid
____
7
___ _
8
___ _
10 ns
t
OLZ
(1)
Output Enable Low to Output in Low-Z 0
____
0
___ _
0
___ _
ns
t
OHZ
(1)
Output Enable High to Output in High-Z
____
6
___ _
6
___ _
8ns
t
OH
Output Hold from Address Change 4
____
4
___ _
5
___ _
ns
t
BE
Byte Enable Low to Output Valid
____
7
___ _
8
___ _
10 ns
t
BLZ
(1)
Byte Enable Low to Output in Low-Z 0
____
0
___ _
0
___ _
ns
t
BHZ
(1)
Byte Enable High to Output in High-Z
____
6
___ _
6
___ _
8ns
t
WC
Write Cycle Time 12
____
15
____
20
____
ns
t
AW
Address Valid to End of Write 9
____
10
____
12
____
ns
t
CW
Chip Select Low to End of Write 9
____
10
____
12
____
ns
t
BW
Byte Enable Low to End of Write 9
____
10
____
12
____
ns
t
AS
Address Set-up Time 0
____
0
___ _
0
___ _
ns
t
WR
Address Hold from End of Write 0
____
0
___ _
0
___ _
ns
t
WP
Write Pulse Width 9
____
10
____
12
____
ns
t
DW
Data Valid to End of Write 7
____
8
___ _
10
___ _
ns
t
DH
Data Hold Time 0
____
0
___ _
0
___ _
ns
t
OW
(1)
Write Enable High to Output in Low-Z 1
____
1
___ _
1
___ _
ns
t
WHZ
(1)
Write Enable Low to Output in High-Z
____
6
___ _
6
___ _
8ns
3210 tbl 10
