6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(7,8)
NOTES:
1. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. 'X' in part numbers indicates power rating (SA or LA).
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7132X20
(1)
7142X20
(1)
Com'l Only
7132X25
(2)
7142X25
(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY Timing (For Master IDT7132 Only)
t
BAA
BUSY Access Time from Address
____
20
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address
____
20
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable
____
20
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
20
____
20 ns
t
WDD
Write Pulse to Data Delay
(2)
____
50
____
50
____
60 ns
t
WH
Write Hold After BUSY
(6)
12
____
15
____
20
____
ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
35
____
35
____
35 ns
t
APS
Arbitration Priority Set-up Time
(3)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(4)
____
25
____
35
____
35 ns
BUSY Timing (For Slave IDT7142 Only)
t
WB
Write to BUSY Input
(5)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(6)
12
____
15
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(2)
____
40
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
30
____
35
____
35 ns
2692 tbl 11a
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
Symbol Parameter Min. Max. Min. Max. Unit
BUSY Timing (For Master IDT7132 Only)
t
BAA
BUSY Access Time from Address
____
30
____
50 ns
t
BDA
BUSY Disable Time from Address
____
30
____
50 ns
t
BAC
BUSY Access Time from Chip Enable
____
30
____
50 ns
t
BDC
BUSY Disable Time from Chip Enable
____
30
____
50 ns
t
WDD
Write Pulse to Data Delay
(2)
____
80
____
120 ns
t
WH
Write Hold After BUSY
(6 )
20
____
20
____
ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
55
____
100 ns
t
APS
Arbitration Priority Set-up Time
(3 )
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(4)
____
50
____
65 ns
BUSY Timing (For Slave IDT7142 Only)
t
WB
Write to BUSY Input
(5 )
0
____
0
____
ns
t
WH
Write Hold After BUSY
(6 )
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(2)
____
80
____
120 ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
55
____
100 ns
2692 tbl 11b