MPC961P Datasheet
8©2016 Integrated Device Technology, Inc. Revision 6, October 4, 2016
OBSOLETE
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% ( 3) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –236 ps to 361 ps relative to PCLK (f = 125 MHz,
V
CC
= 2.5 V):
t
SK(PP)
= [-50 ps...175ps] + [-150 ps...150 ps] +
[(12ps @ -3)...(12ps @ 3)] + t
PD, LINE(FB)
t
SK(PP)
= [-236ps...361ps] + t
PD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure 8
“Max. I/O Jitter versus frequency” can be used for a more
precise timing performance analysis.
Figure 8. Max. I/O Jitter versus Frequency
Power Consumption of the MPC961P
and Thermal Management
The MPC961P AC specification is guaranteed for the
entire operating frequency range up to 200 MHz. The
MPC961P power consumption and the associated long-term
reliability may decrease the maximum frequency limit,
depending on operating conditions such as clock frequency,
supply voltage, output loading, ambient temperature, vertical
convection and thermal conductivity of package and board.
This section describes the impact of these parameters on the
junction temperature and gives a guideline to estimate the
MPC961P die junction temperature and the associated
device reliability. For a complete analysis of power
consumption as a function of operating conditions and
associated long term device reliability refer to the Application
Note AN1545. According the AN1545, the long-term device
reliability is a function of the die junction temperature:
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable MTBF,
the die junction temperature of the MPC961P needs to be
controlled and the thermal impedance of the board/package
should be optimized. The power dissipated in the MPC961P
is represented in equation 1.
Where I
CCQ
is the static current consumption of the
MPC961P, C
PD
is the power dissipation capacitance per
output, C
L
represents the external capacitive output
load, N is the number of active outputs (N is always 27 in case
of the MPC961P). The MPC961P supports driving
transmission lines to maintain high signal integrity and tight
timing parameters. Any transmission line will hide the lumped
capacitive load at the end of the board trace, therefore,
C
L
is zero for controlled transmission line systems and can be
eliminated from equation 1. Using parallel termination output
termination results in equation 2 for power dissipation.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, V
OL
, I
OL
, V
OH
, and I
OH
are a
function of the output termination technique and DC
Q
is the
clock signal duty cycle. If transmission lines are used C
L
is
zero in equation 2 and can be eliminated. In general, the use
of controlled transmission line techniques eliminates the
impact of the lumped capacitive loads at the end lines and
greatly reduces the power dissipation of the device.
Equation 3 describes the die junction temperature T
J
as a
function of the power consumption.
Table 8. Confidence Factor CF
CF Probability of clock edge within the distribution
1 0.68268948
2 0.95449988
3 0.99730007
4 0.99993663
5 0.99999943
6 0.99999999
F_RANGE = 1 F_RANGE = 0
18
16
14
12
10
8
6
4
2
0
50 70 90 110 130 150 170 190
Clock frequency [MHz]
t
jit()
[ps] RMS
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 2.5 V
V
CC
= 3.3 V
Table 9. Die Junction Temperature and MTBF
Junction temperature (C) MTBF (Years)
100 20.4
110 9.1
120 4.2
130 2.0
P
TOT
= [ I
CCQ
+ V
CC
· f
CLOCK
· ( N · C
PD
+ C
L
) ] · V
CC
M
P
TOT
= V
CC
· [ I
CCQ
+ V
CC
· f
CLOCK
· ( N · C
PD
+ C
L
) ] + [ DC
Q
· I
OH
· (V
CC
– V
OH
) + (1 – DC
Q
) · I
OL
· V
OL
]
M
P
T
J
= T
A
+ P
TOT
· R
thja
f
CLOCK,MAX =
C
PD
· N · V
2
CC
1
· [
– (I
CCQ
· V
CC
) ]
R
thja
T
j,MAX
– T
A
Equation 1
Equation 2
Equation 3
Equation 4
