DATASHEET
LVDS Dual-Frequency Programmable VCXO IDT8N4DV85
IDT8N4DV85CCD
REVISION B NOVEMBER 20, 2013 1 ©2013 Integrated Device Technology, Inc.
General Description
The IDT8N4DV85 is a LVDS Dual-Frequency Programmable VCXO
with very flexible frequency and pull-range programming capabilities.
The device uses IDT’s fourth generation FemtoClock® NG
technology for an optimum of high clock frequency and low phase
noise performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm
x 1.55mm package.
The device can be factory-programmed to any two frequencies in the
range of 15.476MHz to 866.67MHz and from 975MHz to 1300 MHz
to the very high degree of frequency precision of 218Hz or better.
The output frequency is selected by the FSEL pin. The extended
temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Features
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1300MHz
Two factory-programmed output frequencies
Frequency programming resolution is 218Hz and better
Absolute pull range (APR) programmable from ±4.5 to ±754.5ppm
One 2.5V or 3.3V LVDS clock output
Output enable control input, LVCMOS/LVTTL compatible
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.47ps (typical)
2.5V or 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm
package
Block Diagram
Pin Assignment
IDT8N4DV85
6-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
6 V
CC
5 nQ
4 Q
VC 1
FSEL 2
GND 3
Q
nQ
OSC
114.285 MHz
÷MINT, MFRAC
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Configuration Register (ROM)
(Frequency, Pull range, Polarity)
23
7
VC
FSEL
Pulldown
A/D
9
÷P
2
IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO
IDT8N4DV85CCD
REVISION B NOVEMBER 20, 2013 2 ©2013 Integrated Device Technology, Inc.
Pin Description and Characteristic Tables
Table 1. Pin Descriptions
Number Name Type Description
1 VC Input VCXO Control Voltage input.
2 FSEL Input
Pulldown
NOTE 1
NOTE 1.Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values
Frequency select pin. See Table 3A for function. LVCMOS/LVTTL interface
levels.
3 GND Power Negative power supply.
4, 5
Q, nQ
Output Differential clock output. LVDS interface levels.
6
V
CC
Power Positive power supply.
Table 2. Pin Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input
Capacitance
FSEL 5.5 pF
VC 10 pF
R
PULLDOWN
Input Pulldown Resistor 50 k
IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO
IDT8N4DV85CCD
REVISION B NOVEMBER 20, 2013 3 ©2013 Integrated Device Technology, Inc.
Function Tables
15.476MHz to 866.67MHz
975MHz to 1300MHz
Principles of Operation
The block diagram consists of the internal 3
RD
overtone crystal and
oscillator which provide the reference clock f
XTAL
of 114.285MHz.
The PLL includes the FemtoClock NG VCO along with the
Pre-divider (P), the feedback divider (M) and the post divider (N). The
P, M, and N dividers determine the output frequency based on the
f
XTAL
reference. The feedback divider is fractional supporting a huge
number of output frequencies. Internal registers are used to hold up
to two different factory pre-set configuration settings. The
configuration is selected via the FSEL pin. Changing the FSEL
control results in an immediate change of the output frequency to the
selected register values. The P, M, and N frequency configurations
support an output frequency range 15.476MHz to 866.67MHz and
975MHz to 1,300MHz.
The devices use the fractional feedback divider with a delta-sigma
modul
ator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator. The output frequency
is determined by the 2-bit pre-divider (P), the feedback divider (M)
and the 7-bit post divider (N). The feedback divider (M) consists of
both a 7-bit integer portion (MINT) and an 18-bit fractional portion
(MFRAC) and provides the means for high-resolution frequency
generation. The output frequency f
OUT
is calculated by
(1)
f
OUT
f
XTAL
1
PN
------------
MINT
MFRAC 0.5+
2
18
-------------------------------------
+=
:
Input
SelectsFSEL
0 (default) Frequency 0
1 Frequency 1
Frequency Configuration
An order code is assigned to each frequency configuration and the
VCXO pull-range programmed by the factory (default frequencies).
For more information on the available default frequencies and order
codes, please see the Ordering Information Section in this document.
For available order codes, see the FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Information document.
For more information on programming capabilities of the device for
custom fre
quency and pull-range configurations, see the FemtoClock
NG Ceramic 5x7 Module Programming Guide.
Table 3A. Output Frequency Range
NOTE 1
NOTE 1.Supported output frequency range. The output frequency
can be programmed to any frequency in this range and to a precision
of 218Hz or better.
Table 3B. Frequency Selection

8N4DV85BC-0173CDI8

Mfr. #:
Manufacturer:
Description:
IC OSC VCXO DUAL FREQ 6-CLCC
Lifecycle:
New from this manufacturer.
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