External Clock
When configured for external clock mode (CLK = 1),
the MAX1136–MAX1139 use the SCL as the conversion
clock. In external clock mode, the MAX1136–MAX1139
begin tracking the analog input on the ninth rising clock
edge of a valid slave address byte. Two SCL clock
cycles later the analog signal is acquired and the con-
version begins. Unlike internal clock mode, converted
data is available immediately after the first four empty
high bits. The device will continuously convert input
channels dictated by the scan mode until given a not
acknowledge. There is no need to re-address the
device with a read command to obtain new conversion
results (see Figure 11).
The conversion must complete in 1ms or droop on the
track-and-hold capacitor will degrade conversion
results. Use internal clock mode if the SCL clock period
exceeds 60µs.
The MAX1136–MAX1139 must operate in external clock
mode for conversion rates from 40ksps to 94.4ksps.
Below 40ksps internal clock mode is recommended
due to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. If AIN_/REF is set to be a reference
input or output (SEL1 = 1, Table 6), AIN_/REF will be
excluded from a multichannel scan. The scanned
results are written to memory in the same order as the
conversion. Read the results from memory in the order
they were converted. Each result needs a 2-byte trans-
mission, the first byte begins with six empty bits during
which SDA is left high. Each byte has to be acknowl-
edged by the master or the memory transmission will
be terminated. It is not possible to read the memory
independently of conversion.
Applications Information
Power-On Reset
The configuration and setup registers (Tables 1 and 2)
will default to a single-ended, unipolar, single-channel
conversion on AIN0 using the internal clock with V
DD
as
the reference and AIN_/REF configured as an analog
input. The memory contents are unknown after power-up.
Automatic Shutdown
Automatic shutdown occurs between conversions when
the MAX1136–MAX1139 are idle. All analog circuits
participate in automatic shutdown except the internal
reference due to its prohibitively long wake-up time.
When operating in external clock mode, a STOP, not-
acknowledge or repeated START, condition must be
issued to place the devices in idle mode and benefit
from automatic shutdown. A STOP condition is not nec-
essary in internal clock mode to benefit from automatic
shutdown because power-down occurs once all con-
version results are written to memory (Figure 10). When
using an external reference or V
DD
as a reference, all
analog circuitry is inactive in shutdown and supply cur-
rent is less than 0.5µA (typ). The digital conversion
results obtained in internal clock mode are maintained
in memory during shutdown and are available for
access through the serial interface at any time prior to a
STOP or a repeated START condition.
When idle the MAX1136–MAX1139 continuously wait
for a START condition followed by their slave address
(see
Slave Address
section). Upon reading a valid
address byte the MAX1136–MAX1139 power-up. The
internal reference requires 10ms to wake up, so when
using the internal reference it should be powered up
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
______________________________________________________________________________________ 17
Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0–AIN2,
the only scan that takes place is AIN2 (MAX1136/MAX1137). When AIN/REF is set to be a reference
input/output, scanning stops at AIN2.
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only
scan that takes place is AIN6 (MAX1138/MAX1139). When AIN/REF is set to be a reference input/
output, scanning stops at selected channel or AIN10.
