Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07
25
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A Address
C Clock
D Input data
H Logic level high
I Instruction (program memory contents)
L Logic level low, or ALE
P PSEN
Q – Output data
R–RD
signal
t Time
V Valid
W– WR
signal
X No longer a valid logic level
Z Float
Examples: t
AVLL
= Time for address valid to ALE low.
t
LLPL
=Time for ALE low to PSEN low.
t
PXIZ
ALE
PSEN
PORT 0
PORT 2
A0–A15 A8–A15
A0–A7 A0–A7
t
AVLL
t
PXIX
t
LLAX
INSTR IN
t
LHLL
t
PLPH
t
LLIV
t
PLAZ
t
LLPL
t
AVIV
SU00006
t
PLIV
Figure 14. External Program Memory Read Cycle
ALE
PSEN
PORT 0
PORT 2
RD
A0–A7
FROM RI OR DPL
DATA IN A0–A7 FROM PCL INSTR IN
P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH
t
WHLH
t
LLDV
t
LLWL
t
RLRH
t
LLAX
t
RLAZ
t
AVLL
t
RHDX
t
RHDZ
t
AVWL
t
AVDV
t
RLDV
SU00025
Figure 15. External Data Memory Read Cycle
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07
26
t
LLAX
ALE
PSEN
PORT 0
PORT 2
WR
A0–A7
FROM RI OR DPL
DATA OUT A0–A7 FROM PCL INSTR IN
P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH
t
WHLH
t
LLWL
t
WLWH
t
AVLL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
SU00026
Figure 16. External Data Memory Write Cycle
012345678
INSTRUCTION
ALE
CLOCK
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
CLEAR RI
VALID VALID VALID VALID VALID VALID VALID VALID
SET TI
SET RI
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
SU00027
1230 4567
Figure 17. Shift Register Mode Timing
V
CC
–0.5
0.45V
0.7V
CC
0.2V
CC
–0.1
t
CHCL
t
CLCL
t
CLCH
t
CLCX
t
CHCX
SU00009
Figure 18. External Clock Drive
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07
27
V
CC
–0.5
0.45V
0.2V
CC
+0.9
0.2V
CC
–0.1
NOTE:
AC inputs during testing are driven at V
CC
–0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at V
IH
min for a logic ‘1’ and V
IL
max for a logic ‘0’.
SU00717
Figure 19. AC Testing Input/Output
V
LOAD
V
LOAD
+0.1V
V
LOAD
–0.1V
V
OH
–0.1V
V
OL
+0.1V
NOTE:
TIMING
REFERENCE
POINTS
For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
V
OH
/V
OL
level occurs. I
OH
/I
OL
±20mA.
SU00718
Figure 20. Float Waveform
SU01413
TYP ACTIVE MODE
MAX IDLE MODE
TYP IDLE MODE
MAX ACTIVE
MODE
I
CC
MAX = 0.9 X FREQ. + 1.1
5
481216
FREQ AT XTAL1 (MHz)
20 24 28 32 36
15
25
30
I
CC
(mA)
10
20
35
Figure 21. I
CC
vs. FREQ
Valid only within frequency specifications of the device under test

P80C32UBPN,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT ROMLESS 40DIP
Lifecycle:
New from this manufacturer.
Delivery:
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