MC74HC4051A, MC74HC4052A, MC74HC4053A
http://onsemi.com
3
LOGIC DIAGRAM
MC74HC4053A
Triple Single–Pole, Double–Position Plus Common Off
X0
12
X1
13
A
11
B
10
C
9
ENABLE
6
X SWITCH
Y SWITCH
X
14
ANALOG
INPUTS/OUTPUTS
CHANNEL-SELECT
INPUTS
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
FUNCTION TABLE – MC74HC4053A
Control Inputs
ON Channels
Enable
Select
CBA
L
L
L
L
L
L
L
L
H
X = Don’t Care
Pinout: MC74HC4053A (Top View)
1516 14 13 12 11 10
21 34567
V
CC
9
8
Y X X1 X0 A B C
Y1 Y0 Z1 Z Z0 Enable V
EE
GND
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
X0
X1
X0
X1
NONE
Y0
2
Y1
1
Y
15
Z0
5
Z1
3
Z
4
Z SWITCH
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
Positive DC Supply Voltage (Referenced to GND)
(Referenced to V
EE
)
– 0.5 to + 7.0
– 0.5 to + 14.0
V
V
EE
Negative DC Supply Voltage (Referenced to GND) – 7.0 to + 5.0 V
V
IS
Analog Input Voltage V
EE
– 0.5 to
V
CC
+ 0.5
V
V
in
Digital Input Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I DC Current, Into or Out of Any Pin ± 25 mA
P
D
Power Dissipation in Still Air, Plastic DIP†
EIAJ/SOIC Package†
TSSOP Package†
750
500
450
mW
T
stg
Storage Temperature Range – 65 to + 150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
260
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
EIAJ/SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND (V
in
or V
out
) V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
