on the upper half of the drive, sourcing current to the gate of the
high-side MOSFET in the external motor-driving bridge, turning
it on. GHx going low turns on the lower half of the drive, sinking
current from the external MOSFET gate circuit to the correspond-
ing Sx pin, turning off the MOSFET.
CA and CB Pins These are the high-side connections for the
bootstrap capacitors and are the positive supply for the high-side
gate drives. The bootstrap capacitors are charged to approxi-
mately V
REG
when the associated output Sx terminal is low.
When the Sx output swings high, the charge on the bootstrap
capacitor causes the voltage at the corresponding Cx terminal to
rise with the output to provide the boosted gate voltage needed
for the high-side MOSFETs.
RDEAD Pin This pin controls internal generation of dead time
during MOSFET switching. Cross-conduction is prevented
by the gate drive circuits, which introduce a dead time, t
DEAD
,
between switching one MOSFET off and the complementary
MOSFET on.
• When an external resistor greater than 3 kΩ is connected be-
tween RDEAD and AGND, the dead time is derived from the
resistor value.
• When RDEAD is connected directly to VDD, t
DEAD
defaults to
a value of 6 μs typical.
Logic Control Inputs
Four low voltage-level digital inputs provide control for the gate
drives. These logic inputs all have a typical hysteresis of 500 mV
to improve noise performance. They provide individual direct
control over each power MOSFET, subject to cross-conduction
prevention, and can be used together to provide fast decay or
slow decay with high-side or low-side recirculation.
AHI, ALO, BHI and BLO Pins These directly control the gate
drives. The xHI inputs control the high-side drives and the xLO
inputs control the low-side drives. Internal lockout logic ensures
that the high-side output drive and low-side output drive cannot
be active simultaneously. Table 1 shows the logic truth table.
RESET Pin This is an active-low input, and when active it
allows the A4957 to enter sleep mode. When RESET
is held low,
the regulator and all internal circuitry are disabled and the A4957
enters sleep mode. Before fully entering sleep mode, there is a
short delay while the regulator decoupling and storage capacitors
discharge. This typically takes a few milliseconds, depending on
the application conditions and component values.
During sleep mode, current consumption from the VBB supply
is reduced to a minimal level. In addition, latched faults and the
corresponding fault flags are cleared. When the A4957 is coming
out of sleep mode, the protection logic ensures that the gate drive
outputs are off until the charge pump reaches its correct operat-
ing condition. The charge pump stabilizes in approximately 3 ms
under nominal conditions.
RESET
can be used also to clear latched fault flags without enter-
ing sleep mode. To do so, hold RESET low for the reset pulse
time, t
RES
.
Note that the A4957 can be configured to start without any exter-
nal logic input. To do so, pull up the RESET pin to V
BB
by means
of an external resistor. The resistor value should be between
20 and 33 kΩ.
Diagnostics
Several diagnostic features are integrated into the A4957 to
provide indication of fault conditions. In addition to system wide
faults such as undervoltage and overtemperature, the A4957 inte-
grates individual bootstrap voltage monitors for each bootstrap
capacitor.
Table 1. Input Logic
Pin Setting
Mode of Operation
RESET xHI xLO GHx GLx Sx
H H L H L H High side MOSFET conducting
H L H L H L Low Side MOSFET conducting
H H H L H L Low Side MOSFET conducting – cross-conduction prevention
H L L L L Z High side and low side off
L x x Z Z Z All gate drives inactive, all MOSFETs off
Full Bridge MOSFET Driver
A4957
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
FAULT Pin This is an open drain output fault flag, which indi-
cates a fault condition by its state, as shown in table 2. It must be
pulled to V
DD
with an external resistor, typically 10 to 47 kΩ.
Fault States
Overtemperature If the junction temperature exceeds the
over-temperature threshold, 170°C typical, the A4957 will enter
the overtemperature fault state and FAULT will go low. The
overtemperature fault state, and FAULT, will only be cleared
when the temperature drops below the recovery level defined by
T
JF
– T
JFHYS
.
No circuitry will be disabled. External control circuits must take
action to limit the power dissipation in some way so as to prevent
overtemperature damage to the A4957 chip and unpredictable
device operation.
VREG Undervoltage VREG supplies the low-side gate driver
and the bootstrap charge current. It is critical to ensure that the
voltages are sufficiently high before enabling any of the outputs.
If the voltage at VREG, V
REG
, drops below the falling VREG
undervoltage lockout threshold, V
REGUVOFF
, then the A4957 will
enter VREG undervoltage, a latched fault state. In this fault state
FAULT will be low, and the outputs will be disabled. The VREG
undervoltage fault state and the fault flags will be cleared on
either an xHI or xLO rising edge or when RESETn is pulled low
for for the reset pulse time, t
RES
.
The VREG undervoltage monitor circuit is active during power-
up, and the A4957 remains in the VREG undervoltage fault state
until VREG is greater than the rising VREG undervoltage lockout
threshold, V
REGUVON
.
Bootstrap Capacitor Undervoltage The A4957 monitors the
voltage across the individual bootstrap capacitors to ensure they
have sufficient charge to supply the current pulse for the high-
side drive. Before a high-side drive can be turned on, the voltage
across the associated bootstrap capacitor must be higher than the
turn-on voltage limit. If this is not the case, then the A4957 will
start a bootstrap charge cycle by activating the complementary
low-side drive. Under normal circumstances, this will charge the
bootstrap capacitor above the turn-on voltage in a few microsec-
onds and the high-side drive will then be enabled.
The bootstrap voltage monitor remains active while the high-side
drive is active and, if the voltage drops below the turn-off volt-
age, a charge cycle will be initiated.
In either case, if there is a fault that prevents the bootstrap capaci-
tor charging, then the charge cycle will timeout, FAULT will be
low, and the outputs will be disabled. The bootstrap undervoltage
fault state remains latched until RESET is set low.
VDD Undervoltage The logic supply at VDD is monitored
to ensure correct logical operation. If the voltage at VDD, V
DD
,
drops below the falling VDD undervoltage lockout threshold,
V
DDUVOFF
, then the A4957 will enter the VDD undervoltage
fault state. In this fault state, FAULT will be low, and the outputs
will be disabled. In addition, because the state of other reported
faults cannot be guaranteed, all fault states are reset and replaced
by a VDD undervoltage fault state. For example, a VDD under-
voltage will reset an existing boostrap undervoltage fault condi-
tion and replace it with a VDD undervoltage fault. The VDD
undervoltage fault state and the fault flag will be cleared when
V
DD
rises above the rising VDD undervoltage lockout threshold
defined by V
DDUVOFF
+V
DDUVHYS
.
The VDD undervoltage monitor circuit is active during power-up,
and the A4957 remains in the VDD undervoltage fault state until
V
DD
is greater than the rising VDD undervoltage lockout thresh-
old, V
DDUVOFF
+V
DDUVHYS
.
Full Bridge MOSFET Driver
A4957
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Table 2. Fault Definitions
FAULT Pin Setting Fault Description Disable Outputs* Fault Latched Fault Reset Action
High No Fault No N.A.
Low Overtemperature No No N.A.
Low VDD undervoltage Yes No N.A.
Low VREG undervoltage Yes Yes
Rising Edge on xHI or xLO
or Reset
Low Bootstrap undervoltage Yes Yes
Rising Edge on xHI or xLO
or Reset
*”Yes” indicates all gate drives low, and all MOSFETs off.
Dead Time
To prevent cross-conduction (shoot-through) in any phase of the
power MOSFET bridge, it is necessary to have a dead time delay,
t
DEAD
, between a high-side or low-side turn-off and the next
complementary turn-on event. The potential for cross-conduction
occurs when any complementary high-side and low-side pair
of MOSFETs are switched at the same time; for example, when
using synchronous rectification or after a bootstrap capacitor
charging cycle. In the A4957, the dead time for both phases is set
by a single dead-time resistor, R
DEAD
, between the RDEAD and
AGND pins.
For R
DEAD
between 3 and 240 kΩ at 25°C, the value of t
DEAD
(ns), can be approximated by:
t
DEAD
50 +
1.2 + (
200 /
R
DEAD
)
7200
where R
DEAD
is in kΩ. Figure 1 illustrates the relationship of
t
DEAD
and R
DEAD
, with the greatest accuracy obtained for values
of R
DEAD
between 6 and 60 kΩ.
The I
DEAD
current can be estimated by:
I
DEAD
R
DEAD
1.2
The maximum dead time of 6 μs typical can be set by connecting
the RDEAD pin directly to VDD.
Alternatively, the dead time in the A4957 can be disabled by
connecting the RDEAD pin directly to GND. In this case the
required dead time must be supplied by the external controller.
The choice of power MOSFET and external series gate resistance
determine the selection of the dead-time resistor, R
DEAD
. The
dead time should be long enough to ensure that one MOSFET
in a phase has stopped conducting before the complementary
MOSFET starts conducting. This should also take into account
the tolerance and variation of the MOSFET gate capacitance, the
series gate resistance, and the on-resistance of the A4957 internal
drives.
Dead time will be present only if the on-command for one
MOSFET occurs within t
DEAD
after the off-command for its
complementary MOSFET. In the case where one side of a phase
drive is permanently off, for example when using diode rectifica-
tion with slow decay, then the dead time will not occur. In this
case the gate drive will turn on within the specified propagation
delay after the corresponding phase input goes high. (Refer to the
Gate Drive Timing diagrams.)
Braking
The A4957 can be used to perform dynamic braking by forc-
ing all low-side MOSFETs on and all high-side MOSFETs off
(ALO=BLO=1, AHI=BHI=0) or, conversely, by forcing all low-
side off and all high-side on (ALO=BLO=0, AHI= BHI=1). This
effectively short-circuits the back EMF of the motor, creating a
breaking torque.
During braking, the load current can be approximated by:
I
BRAKE
R
L
V
bemf
where V
bemf
is the voltage generated by the motor and R
L
is the
resistance of the phase winding.
Care must be taken during braking to ensure that maximum rat-
ings of the power MOSFETs are not exceeded. Dynamic braking
is equivalent to slow decay with synchronous rectification.
Figure 1. Dead time versus values of R
DEAD
(full range).
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0 50 100 150 200
R
DEAD
(k)
t
DEAD
(s)
250 300 350 400
Full Bridge MOSFET Driver
A4957
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Application Information

APEK4957SES-01-T-DK

Mfr. #:
Manufacturer:
Description:
BOARD EVAL FOR A4957SES
Lifecycle:
New from this manufacturer.
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