74LVT374, 74LVTH374 — Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVT374, 74LVTH374 Rev. 1.5.0
January 2008
74LVT374, 74LVTH374
Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
Features
Input and output interface capability to systems at
5V V
CC
Bus-Hold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH374),
also available without bushold feature (74LVT374)
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink –32mA/+64mA
Functionally compatible with the 74 series 374
Latch-up performance exceeds 500mA
ESD performance:
– Human-body model
>
2000V
– Machine model
>
200V
– Charged-device model
>
1000V
General Description
The LVT374 and LVTH374 are high-speed, low-power
octal D-type flip-flops featuring separate D-type inputs
for each flip-flop and 3-STATE outputs for bus-oriented
applications. A buffered Clock (CP) and Output Enable
(OE
) are common to all flip-flops.
The LVTH374 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal flip-flops are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT374 and
LVTH374 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
74LVT374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVT374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT374MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74LVTH374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVTH374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH374MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVT374, 74LVTH374 Rev. 1.5.0 2
74LVT374, 74LVTH374 — Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
Connection Diagram
Pin Description
Functional Description
The LVT374 and LVTH374 consist of eight edge-
triggered flip-flops with individual D-type inputs and
3-STATE true outputs. The buffered clock and buffered
Output Enable are common to all flip-flops. The eight flip-
flops will store the state of their individual D inputs that
meet the setup and hold time requirements on the LOW-
to-HIGH Clock (CP) transition. With the Output Enable
(OE
) LOW, the contents of the eight flip-flops are avail-
able at the outputs. When the OE
is HIGH, the outputs
go to the high impedance state. Operation of the OE
input does not affect the state of the flip-flops.
Logic Symbols
IEEE/IEC
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
O
o
=
Previous O
o
before HIGH-to-LOW of CP
Pin Names Description
D
0
–D
7
Data Inputs
CP Clock Pulse Input
OE
3-STATE Output Enable Input
O
0
–O
7
3-STATE Outputs
Inputs Outputs
D
n
CP OE O
n
HLH
LLL
XLL O
o
XXH Z
©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVT374, 74LVTH374 Rev. 1.5.0 3
74LVT374, 74LVTH374 — Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.

74LVT374WM

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Flip Flops Oct D-Type Flip-Flop
Lifecycle:
New from this manufacturer.
Delivery:
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