MAX5911/MAX5912
-48V Simple Swapper Hot-Swap Switches
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heat dissipation properties, and always solder all of its
V
IN
pins to a large section of circuit board copper.
Logic Control
The enable input responds to +3.3V logic signals and
will force the internal FET off if it is pulled low. This fea-
ture allows the host to disconnect the load from the
power bus if required. Additionally, all fault conditions
that latch the internal FET off must be cleared by puls-
ing ENABLE low for at least 200ns, then reasserting
ENABLE before normal operation can resume.
GATE Connections
GATE connects to the gate of the internal N-channel
power MOSFET. Normally this pin should be left open
circuit. To slow down the voltage ramp at V
OUT
, con-
nect capacitors from GATE to V
OUT
and V
IN
. Size the
capacitors so that the GATE to V
IN
capacitor is ten
times the size of the GATE to V
OUT
capacitor. This
technique to slow down the output voltage ramp will
also cause the output discharge time to increase if the
capacitor values exceed about 1nF. Additionally, this
technique will cause the time delay for a power-not-
good fault to increase.
FAULT
Output
The FAULT output is open-drain and is pulled low if the
MAX5911/MAX5912 detect an undervoltage fault, a
thermal fault, a power-not-good fault, or a zero-current
fault. See the Normal Operation section for specific
details of fault operation. Connect FAULT to the logic
supply with a pullup resistor; 3.3kΩ is sufficient in most
cases.
Changing the Undervoltage
Lockout Setting
The UVLO value defaults to -28V if the UVLO pin is left
open circuit. The lockout voltage can be changed with
a resistive divider. Connect the divider from V
IN
to
AGND, and connect the center node of the divider to
the UVLO pin. Figure 2 shows an example circuit. Use
R1 ≤ 10kΩ, then calculate R2 using:
where V
IN(UVLO)
is the desired lockout voltage.
Chip Information
TRANSISTOR COUNT: 1021
PROCESS: BiCMOS
.
