IDT
/ ICS
3.3V LVPECL FREQUENCY SYNTHESIZER 7 ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW
SCOPE
Qx
nQx
LVPECL
V
EE
2V
-1.3V± 0.165V
tsk(o)
nFOUTx
FOUTx
nFOUTy
FOUTy
CYCLE-TO-CYCLE JITTER
PERIOD JITTER
FOUTx
tcycle n tcycle n+1
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
t
cycle n+1
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10
-7
)% of all measurements
Histogram
nFOUTx
FOUTx
nFOUTx
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
OUTPUT RISE/FALL TIME
V
EE
V
CC
,
V
CCO
V
CCA
2V
PARAMETER MEASUREMENT INFORMATION
20%
80%
80%
20%
t
R
t
F
V
SWING
FOUTx
nFOUTx
IDT
/ ICS
3.3V LVPECL FREQUENCY SYNTHESIZER 8 ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Table 8. Common SANs Application Frequencies
Table 9. Configuration Details for SANs Applications
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS8432-51 pro-
vides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. V
CC
, V
CCA
and V
CCO
should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin.
Figure 2
illustrates this for a generic V
CC
pin and also shows that
V
CCA
requires that an additional 10Ω resistor along with a 10µF
bypass capacitor be connected to the V
CCA
pin.
FIGURE 2. POWER SUPPLY FILTERING
10Ω
V
CCA
10 μF
.01μF
3.3V
.01μF
V
CC
ygolonhceTtcennocretnIetaRkcolC
SEDRESotycneuqerFecnerefeR
)zHM(
ycneuqerFlatsyrC
)zHM(
tenrehtEtibagiGzHG52
.152.651,052,52152135.91,52
lennahCerbiF
zHG5260.11CF
zHG0521.22CF
5218.231,521.35,52.60152,5265106.61
dnabin
ifnIzHG5.2052,52152
POWER SUPPLY FILTERING T ECHNIQUES
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the
elements within a SAN. The tables below lists the common
frequencies used as well as the settings for the ICS8432-51 to
generate the appropriate frequency.
tcennocretnI
ygolonhceT
ycneuqerFlatsyrC
)zHM(
15-2348SCI
ycneuqerFtuptuO
SEDRESot
)zHM(
15-2348SCI
sgnitteSN&
M
8M7M6M5M4M3M2M1M0M1N0N
tenrehtEtibagiG
52521 000010100 10
52052 0000101000 1
5252.651 00001100110
52135.9152.651 000100000 10
1lennahCrebiF
52521.35 00001000111
5252.601 00001000110
2lennahCrebiF526510
6.615218.231 00010000010
dnabinifnI
52521 000010100 10
52052 0000101000 1
IDT
/ ICS
3.3V LVPECL FREQUENCY SYNTHESIZER 9 ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FIGURE 3. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The ICS8432-51 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 3
below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in
Figure 4.
The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
FIGURE 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTA L _I N
XTA L _OU T
.1uf
Rs
C1
22p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN

ICS8432BY-51

Mfr. #:
Manufacturer:
Description:
IC SYNTHESIZER LVPECL 32-LQFP
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