8
AMGP
6445
YWWDNN
1 2 3
48
7 6 5
GND GND
GND GND
AVAGO
Tech
5 x 5 mm
Q104
Evaluation Board Description
Table 4. Typical Test Conditions
Pin
Vd1,2 5 V Drain Supply Voltage
Idq = Id1 + Id2 700 mA Quiescent Drain Current
Vg1, 2 -0.6 Gate Supply Voltage
Notes:
Vg1 and Vg2 of -0.6 V may need be adjusted to obtain Idsq = 700 mA.
Recommended turn on sequence
Apply Vg1 and Vg2 at -1.5 V
Apply Vd1 and Vd2 at 0 V
Increase Vd to 5 V
Increase Vg of -1.5 V to approximately -0.6 V to obtain
Idsq = 0.7 A
Apply RF Input not to exceed 20 dBm
Turn o in reverse order
Demo board circuit
RF_IN RF_OUT
Vdd
8
1 2
3
4
5
67
100 pF >
0.1 PF
100 pF
>
0.1 PF
Vgg
DET_0
DET_R
Integrated Detector Application Circuit
To obtain temperature compensated RF power detector
function, a di erential voltage between DET_R and DET_O
must be obtained by using an operational ampli er in a
di erential mode con guration as shown in Figure 19.
Figure 19.
Figure 20.
+5 V
DET_0
+5 V
+
–
–5 V
DET_R
100 K: 100 K:
Vout = DET_R – DET_0
10 K:
10 K:
10 K:
10 K:
