MC74VHC08DR2G

© Semiconductor Components Industries, LLC, 2014
October, 2017 − Rev. 11
1 Publication Order Number:
MC74VHC08/D
MC74VHC08
Quad 2-Input AND Gate
The MC74VHC08 is an advanced high speed CMOS 2−input AND
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
High Speed: t
PD
= 4.3 ns (Typ) at V
CC
= 5.0 V
Low Power Dissipation: I
CC
= 2.0 mA (Max) at T
A
= 25°C
High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: V
OLP
= 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 24 FETs or 6 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
3
Y1
1
A1
Figure 1. Logic Diagram
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
Y = AB
Figure 2. Pinout: 14−Lead Packages
1314 12 11 10 9 8
21 34567
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
(Top View)
SOIC−14
D SUFFIX
CASE 751A
TSSOP
DT SUFFIX
CASE 948G
www.onsemi.com
(Note: Microdot may be in either location)
MARKING
DIAGRAMS
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
L
L
L
H
Y
VHC
08
ALYW
1
14
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or = Pb−Free Package
1
14
VHC08G
AWLYWW
1
14
1
14
MC74VHC08
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage –0.5 to +7.0 V
V
in
DC Input Voltage –0.5 to +7.0 V
V
out
DC Output Voltage –0.5 to V
CC
+0.5 V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air, SOIC Package
TSSOP Package
500
450
mW
T
stg
Storage Temperature –65 to +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature −55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3 V ±0.3 V
V
CC
= 5.0 V ±0.5 V
0
0
100
20
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Symbo
l
Parameter Test Conditions
V
CC
V
T
A
= 25°C T
A
= −55°C to 125°C
Unit
Min Typ Max Min Max
V
IH
Minimum High−Level
Input Voltage
2.0
3.0 to 5.5
1.50
V
CC
x 0.7
1.50
V
CC
x 0.7
V
V
IL
Maximum Low−Level
Input Voltage
2.0
3.0 to 5.5
0.50
V
CC
x 0.3
0.50
V
CC
x 0.3
V
V
OH
Minimum High−Level
Output Voltage
V
in
= V
IH
or V
IL
I
OH
= −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
V
V
in
= V
IH
or V
IL
I
OH
= −4.0 mA
I
OH
= −8.0 mA
3.0
4.5
2.58
3.94
2.48
3.80
V
OL
Maximum Low−Level
Output Voltage
V
in
= V
IH
or V
IL
I
OL
= 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
I
OL
= 4.0 mA
I
OL
= 8.0 mA
3.0
4.5
0.36
0.36
0.44
0.44
I
in
Maximum Input
Leakage Current
V
in
= 5.5 V or GND 0 to 5.5 ±0.1 ±1.0
mA
I
CC
Maximum Quiescent
Supply Current
V
in
= V
CC
or GND 5.5 2.0 20.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74VHC08
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3
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0 ns)
Symbo
l
Parameter Test Conditions
T
A
= 25°C T
A
= −55°C to 125°C
Unit
Min Typ Max Min Max
t
PLH
,
t
PHL
Maximum Propagation
Delay,
A or B to Y
V
CC
= 3.3 ± 0.3 V C
L
= 15 pF
C
L
= 50 pF
6.2
8.7
8.8
12.3
1.0
1.0
10.5
14.0
ns
V
CC
= 5.0 ± 0.5 V C
L
= 15 pF
C
L
= 50 pF
4.3
5.8
5.9
7.9
1.0
1.0
7.0
9.0
C
in
Maximum Input
Capacitance
4 10 10 pF
C
PD
Power Dissipation Capacitance (Note 1)
Typical @ 25°C, V
CC
= 5.0 V
pF
18
1. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/4 (per gate). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0 ns, C
L
= 50 pF, V
CC
= 5.0 V)
Symbo
l
Characteristic
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.3 0.8 V
V
OLV
Quiet Output Minimum Dynamic V
OL
−0.3 −0.8 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
Figure 3. Switching Waveforms
Y
A or B
50% V
CC
t
PLH
t
PHL
GND
V
CC
50%
C
L
*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
Figure 5. Input Equivalent Circuit
INPUT
ORDERING INFORMATION
Device Package Shipping
MC74VHC08DR2G SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
MC74VHC08DTR2G
TSSOP−14
(Pb−Free)
2500 Units / Tape & Reel
NLV74VHC08DTRG*
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable

MC74VHC08DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Logic Gates 2-5.5V Quad 2-Input
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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