LT1947
7
1947fa
To best understand operation of the LT1947, please refer
to the LT1947 Block Diagram. The device contains two
switching regulators, a timer and a high side switch. Three
outputs can be generated: an adjustable AV
DD
output, a
charge-pumped inversion of the AV
DD
output called V
OFF
,
and a time delayed adjustable output called V
ON
. Q3 keeps
V
ON
off for an externally set time interval, set by a capacitor
connected to the C
T
pin.
The switching frequency of both switchers is 3MHz, set
internally. The switchers are current mode and are inter-
nally compensated. The main AV
DD
switcher is current
limited at 1.1A, while the second V
ON
switcher is limited to
350mA. They share the same 1.26V reference voltage.
When the input voltage is below approximately 2.7V, an
undervoltage lockout circuit disables switching.
When AV
DD
is less than its final voltage, Q4 is turned on,
holding the C
T
pin at ground. When AV
DD
reaches final
value, Q4 lets go of the C
T
pin, allowing the 5.5µA current
source to charge the external capacitor, C
T
. When the
voltage on the C
T
pin reaches 1.28V, Q3 turns on,
connecting V
O2
to V
ON
. Capacitor value can be calculated
using the following formula:
C = (5.5µA • t
DELAY
)/1.28V
A 10nF capacitor results in approximately 2.3ms of delay.
Layout Hints
The high speed operation of the LT1947 mandates careful
attention to layout for proper performance. Be sure to keep
input capacitor C1 as close as possible to the IC and
minimize trace area and length at the SW and FB pins.
Always use a ground plane under the switching regulator
to minimize interplane coupling. Figure 2 shows the rec-
ommended component placement.
The exposed pad of the MSE package must be soldered to
the PCB and electrically connected to ground. Thermal
vias to a large ground plane will lower the thermal resis-
tance.
Soft-Start
For applications requiring soft-start, a circuit consisting of
R
SS
and C
SS
tied to the SHDN pin can be used, as shown
in Figure 3. For a combination of 33.2k/33nF, AV
DD
rises
to its final value in approximately 3ms.
OPERATIO
U
Figure 2. Recommended Component Placement
C1
C3
L2 D2
V
ON
V
IN
1
2
3
4
5
10
9
8
7
6
LT1947
C6
L1
D1
D3 D4
C5
R1
R4
R2
R3
GND
C4
C2
V
OFF
AV
DD
V
IN
SHDN
GND
1947 F02
