Philips Semiconductors Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
57
XRAMB
7 6 5 4 3 2 1 0
a15 – a9 of XRAM Base Address XRE
XRE XRAM Enable bit, resets to ‘0’.
0 = XRAM disabled
1 = XRAM enabled
MIF Control and Configuration Registers
MIFCNTL (SFR)
D Address: SFR 495h
MIFCNTL
7 6 5 4 3 2 1 0
– – – WAITD BUSD – – –
WAITD Wait Disable
0 = Wail enabled
1 = Wait disabled
BUSD External Access Disable
0 = enable
1 = disable
MIFBTRL (Memory Interface Bus Timing Register Low, MMR)
D Address: MMR base + 292h
D Access: Read, write, byte or word
D Reset value: EFh
MIFBTRL
7 6 5 4 3 2 1 0
WM1 WM0 ALEW – CR1 CR0 CRA1 CRA0
MIFBTRH (Memory Interface Bus Timing Register High, MMR)
D Address: MMR base + 294h
D Access: Read, write, byte or word
D Reset value: FFh
MIFBTRH
7 6 5 4 3 2 1 0
DW1 DW0 DWA1 DWA0 DR1 DR0 DRA1 DRA0
Note: The two MMRs MIFBTRL and MIFBTRH are not to be
confused with the two SFRs BTRL and BTRH, which control the
operation of the BIU, not the MIF. In order for the MIF to function
properly, the contents of BTRL and BTRH have to be set at a fixed
configuration on reset, by User application software, similar to the
treatment for the XA-SCC MIF.
Bus Arbitration
Bus arbitration is done on an “alternate” policy. After a DMA bus
access, the CPU will get the bus if requested. After a CPU bus
access, the DMA will get the bus if requested. A burst access from
the CPU cannot be interrupted by a DMA bus access.
SPI Port
The on–chip SPI Port uses the following Memory Mapped Registers:
SPICFG (MMR)
D Address: MMR base + 260h
D Access: Read, write, byte or word
D Reset value: 00h
SPICFG
7 6 5 4 3 2 1 0
SPCP Rsvd Rsvd Rsvd SPC3 SPC2 SPC1 SPC0
SPCP SPICLK Polarity
0 = inverted SPICLK
1 = normal SPICLK
Rsvd Reserved bits, only write zeros.
SPC3 – SPC0 SPICLK timing
SPICLK = (CClk) / 4 (SPICFG[3:0] + 1)
SPIDATA (MMR)
D Address: MMR base + 262h
D Access: Read, write, byte or word
D Reset value: 00h
SPIDATA
7 6 5 4 3 2 1 0
Data
SPICS (MMR)
D Address: MMR base + 263h
D Access: Read, write, byte or word
D Reset value: 00h
