Evaluate: MAX1002/MAX1003
External Clock Operation
The MAX1002/MAX1003 EV kits can be converted to
drive the ADCs from an external clock source. This
involves removing the external resonator components
from the VCO circuit and adding a few new compo-
nents. Table 4 lists the EV kit changes required to con-
vert the board to accept an external clock source. The
resulting schematic is shown in Figure 4.
The new 49.9Ω value of R3 shown in Figure 4 provides
proper termination for a 50Ω external signal generator.
AC-coupling capacitor C6 couples the external clock
signal to the MAX1002/MAX1003 oscillator circuitry at
TNK+ (pin 9). R2 and C7 ensure that the impedance at
both ports of the oscillator is balanced. After all modifi-
cations are complete, connect an external clock source
to the BNC connector on the EV kit marked CLOCK
OVERDRIVE. The recommended clock amplitude is
1Vp-p; however, the ADC operates correctly with as lit-
tle as 100mVp-p or up to 2.5Vp-p on CLOCK OVER-
DRIVE.
The external clock source should have low phase noise
for best dynamic performance. A low-phase-noise
sine-wave oscillator serves this purpose well. A square-
wave clock source is not necessary to drive the
MAX1002/MAX1003. The devices contain sufficient
gain to amplify even a low-level-input sine wave to drive
the ADC comparators, while ensuring excellent dynam-
ic performance.
Digital Outputs
The TTL/CMOS-compatible digital outputs are present-
ed in parallel from both I and Q channels at connector
J1. The data format is offset binary with the MSB as D5
and the LSB as D0. The row of pins closest to the
board edge is digital output ground (OGND), while the
data bits occupy the inside row. Located in the middle
of the connector is the pin for the output clock labeled
DCLK. This signal can be used to latch the parallel out-
put data for capture into a logic analyzer or external
DSP circuitry. Both digital outputs are updated on
DCLK’s rising edge (see the timing diagram in the
MAX1002 or MAX1003 data sheet).
_____________Layout Considerations
The MAX1002/MAX1003 EV kit layouts have been opti-
mized for high-speed signals. Careful attention has
been given to grounding, power-supply bypassing, and
signal-path layout to minimize coupling between the
analog and digital sections of the circuit. For example,
the ground plane has been removed under the tank cir-
cuitry to reduce stray capacitive loading on the relative-
ly small capacitors required in the external resonant
tank formed by C5, L1, and D1. Other layout considera-
tions are detailed in the following sections.
Power Supplies and Grounding
The EV kits feature separate analog and digital power
supplies and grounds for best dynamic performance. A
thin trace located on the backside of the circuit board
near the VCC power-supply connector ties the analog
and output ground planes together. This trace can be
cut if the power-supply grounds are referenced else-
where.
Referencing analog and digital grounds together at a
single point usually avoids ground loops and corruption
of sensitive analog circuitry by noise from the digital
outputs. If the ground trace on the backside of the
board is cut, observe the absolute maximum ratings
between the two grounds.
MAX1002/MAX1003 Evaluation Kits
4 _______________________________________________________________________________________
5pF capacitor (MAX1003),
22pF capacitor (MAX1002)
Clock input BNC
connector
DESCRIPTION
47pF capacitors
COMPONENT
Clock Overdrive
C6, C7
C5
Remove
Add
MODIFICATION
Replace with
0.01µF capaci-
tors
10kΩ resistor
220nH inductor
Remove
Remove
47kΩ resistors
Replace with
49.9Ω resistors
L1
R2, R3
R1
Varactor diode RemoveD1
Table 4. External Clock Source EV Kit
Modifications
