TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 10 November 2017 17 of 32
NXP Semiconductors
TJA1043
High-speed CAN transceiver
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2] Not tested in production; guaranteed by design.
[3] The test circuit used to measure the bus output voltage symmetry (which includes C
SPLIT
) is shown in Figure 12.
11. Dynamic characteristics
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2] See Figure 8
.
[3] Minimum value of 0.8ms required according to SAE J2284; 0.3ms is allowed according to ISO11898-2:2016 for legacy devices.
Table 9. Dynamic characteristics;
V
CC
= 4.5 V to 5.5 V; V
IO
= 2.8 V to V
CC
; V
BAT
=4.5Vto40V; R
L
=60
; T
vj
=
40
Cto+150
C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device
[1]
.
Symbol Parameter Conditions Min Typ Max Unit
Timing characteristics; Figure 7
t
d(TXD-busdom)
delay time from TXD to bus dominant Normal mode - 70 - ns
t
d(TXD-busrec)
delay time from TXD to bus recessive Normal mode - 90 - ns
t
d(busdom-RXD)
delay time from bus dominant to RXD Normal or Listen-only mode - 60 - ns
t
d(busrec-RXD)
delay time from bus recessive to RXD Normal or Listen-only mode - 70 - ns
t
d(TXDL-RXDL)
delay time from TXD LOW to RXD LOW Normal mode 40 - 240 ns
t
d(TXDH-RXDH)
delay time from TXD HIGH to RXD HIGH Normal mode 40 - 240 ns
t
det(uv)
undervoltage detection time 100 - 350 ms
t
rec(uv)
undervoltage recovery time 1 - 5 ms
t
bit(bus)
transmitted recessive bit width t
bit(TXD)
= 500 ns
[2]
435 - 530 ns
t
bit(TXD)
= 200 ns
[2]
155 - 210 ns
t
bit(RXD)
bit time on pin RXD t
bit(TXD)
= 500 ns
[2]
400 - 550 ns
t
bit(TXD)
= 200 ns
[2]
120 - 220 ns
t
rec
receiver timing symmetry t
bit(TXD)
= 500 ns 65 - +40 ns
t
bit(TXD)
= 200 ns 45 - +15 ns
t
to(dom)TXD
TXD dominant time-out time V
TXD
=0V
[3]
0.4 0.6 1.5 ms
t
to(dom)bus
bus dominant time-out time V
O(dif)
> 0.9 V 0.4 0.6 1.5 ms
t
h
hold time from issuing go-to-sleep
command to entering Sleep
mode
20 35 50 s
t
wake(busdom)
bus dominant wake-up time Standby or Sleep mode;
V
BAT
=12V
0.5 1.75 3 s
t
wake(busrec)
bus recessive wake-up time Standby or Sleep mode;
V
BAT
=12V
0.5 1.75 3 s
t
to(wake)bus
bus wake-up time-out time 0.5 - 2 ms
t
wake
wake-up time in response to a falling or rising
edge on pin WAKE; Standby or
Sleep mode
52550s
