74F164ASJX

© 2000 Fairchild Semiconductor Corporation DS010613 www.fairchildsemi.com
October 1989
Revised October 2000
74F164A Serial-In, Parallel-Out Shift Register
74F164A
Serial-In, Parallel-Out Shift Register
General Description
The 74F164A is a high-speed 8-bit serial-in/parallel-out
shift register. Serial data is entered through a 2-input AND
gate synchronous with the LOW-to-HIGH transition of the
clock. The device features an asynchronous Master Reset
which clears the register, setting all outputs LOW indepen-
dent of the clock. The 74F164A is a faster version of the
74F164.
Features
Typical shift frequency of 90 MHz
Asynchronous Master Reset
Gated serial data input
Fully synchronous data transfers
74F164A is a faster version of the 74F164
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F164ASC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F164ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F164APC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2
74F164A
Unit Loading/Fan Out
Functional Description
The 74F164A is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
HIGH Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q
0
the log-
ical AND of the two data inputs (A B) that existed before
the rising clock edge. A LOW level on the Master Reset
(MR
) input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
Mode Select Table
H(h) = HIGH Voltage Levels
L(l) = LOW Voltage Levels
X = Immaterial
q
n
= Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
A, B Data Inputs 1.0/1.0 20 µA/0.6 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20
µA/0.6 mA
MR
Master Reset Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
Q
0
Q
7
Outputs 50/33.3 1 mA/20 mA
Operating Inputs Outputs
Mode MR
AB
Q
0
Q
1
–Q
7
Reset (Clear) L X X L L-L
Hl lLq
0
q
6
Shift H l h L q
0
q
6
Hh l L q
0
q
6
HhhHq
0
q
6
3 www.fairchildsemi.com
74F164A
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature 65°C to +150°C
Ambient Temperature under Bias
55°C to +125°C
Junction Temperature under Bias
55°C to +150°C
V
CC
Pin Potential to Ground Pin 0.5V to +7.0V
Input Voltage (Note 1)
0.5V to +7.0V
Input Current (Note 1)
30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output
0.5V to V
CC
3-STATE Output 0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambient Temperature 0
°C to +70°C
Supply Voltage
+4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage 1.2 V Min I
IN
= 18 mA
V
OH
Output HIGH 10% V
CC
2.5
VMin
I
OH
= 1 mA
Voltage 5% V
CC
2.7 I
OH
= 1 mA
V
OL
Output LOW Voltage 10% V
CC
0.5 V Min I
OL
= 20 mA
I
IH
Input HIGH
5.0 µAMaxV
IN
= 2.7V
Current
I
BVI
Input HIGH Current
7.0 µAMaxV
IN
= 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
I
ID
= 1.9 µA
Test All other pins grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All other pins grounded
I
IL
Input LOW Current 0.6 mA Max V
IN
= 0.5V
I
OS
Output Short-Circuit Current 60 150 mA Max V
OUT
= 0V
I
CC
Power Supply Current 35 55 mA Max CP = HIGH
MR = GND, A, B = GND

74F164ASJX

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Counter Shift Registers Shift Register
Lifecycle:
New from this manufacturer.
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