SL2309SI-1HT Datasheet SL2309SC-1H, SL2309SI-1H, SL2309SC-1HT | P4-P6

Rev 2.0, May 12, 2008 Page 4 of 12

SL2309

0

5 10

15 20

25 30-30

-25

-20

-5

-10

-15

1500

1000

500

-500

-1500

-1000

0

Output Load Difference: FBK Load – CLKA or CLKB Load (pF)

CLKIN Input to CLKA or CLKB Delay (ps)

Figure 1. CLKIN Input to CLK A and B Delay

(In terms of load difference between CLKOUT and CLK A and B)

S2

S1

Clock A1-A4

Clock B1-4

CLKOUT

Output Source

PLL Status

0

Tri-state

Driven

PLL

On

0

1

Driven

Tri-state

Driven

PLL

On

1

0

Driven

Reference

Off

1

Driven

PLL

On

Table 2. Select Input Decoding

Not Recommended

for New Designs

Rev 2.0, May 12, 2008 Page 5 of 12

SL2309

Absolute Maximum Ratings

Operating Conditions: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades

Description

Condition

Min

Max

Unit

Supply voltage, VDD

– 0.5

4.6

V

All Inputs and Outputs

– 0.5

VDD+0.5

V

Ambient Operating Temperature

In operation, C-Grade

0

70

°C

Ambient Operating Temperature

In operation, I-Grade

– 40

85

°C

Storage Temperature

No power is applied

– 65

150

°C

Junction Temperature

In operation, power is applied

–

125

°C

Soldering Temperature

–

260

°C

ESD Rating (Human Body Model)

JEDEC22-A114D

-4,000

4,000

V

ESD Rating (Charge Device Model)

JEDEC22-C101C

-1,500

1,500

V

ESD Rating (Machine Model)

JEDEC22-A115D

-250

250

V

Latch-up

125°C

-200

200

mA

Symbol

Description

Condition

Min

Max

Unit

VDD

3.3V Supply Voltage

3.3V+/-10%

3.0

3.6

V

TA

Operating Temperature(Ambient)

Commercial

0

70

°C

Industrial

– 40

85

°C

CLOAD

Load Capacitance

10 to 140 MHz, -1H high drive

All active PLL modes

–

15

pF

10 to 100 MHz, -1H high drive

All active PLL modes

–

30

pF

10 to 100MHz, -1 standard drive

All active PLL modes

–

15

pF

10 to 66MHz, -1 standard drive

All active PLL modes

–

30

pF

CIN

Input Capacitance

S1, S2 and CLKIN pins

–

7

pF

tpu

Power-up Time

Power-up time for all VDDs to reach

minimum VDD voltage (VDD=3.0V).

0.05

100

ms

CLBW

Closed-loop bandwidth

3.3V, (typical)

1.2

MHz

ZOUT

Output Impedance

3.3V, (typical), -1H high drive

22

Ω

3.3V, (typical), -1 standard drive

32

Ω

Not Recommended

for New Designs

Rev 2.0, May 12, 2008 Page 6 of 12

SL2309

DC Electrical Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades

Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades

Symbol

Description

Condition

Min

Max

Unit

VDD

Supply Voltage

3.0

3.6

V

VIL

Input LOW Voltage

CLKIN, S2 and S1 Pins

–

0.8

V

VIH

Input HIGH Voltage

CLKIN, S2 and S1 pins

2.0

VDD+0.3

V

IIL

Input LOW Current

CLKIN, S2 and S1 Pins, 0 < VIN < 0.8V

–

25

µA

IIH

Input HIGH Current

CLKIN, S2 and S1 Pins, VIN = VDD

–

50

µA

VOL

Output LOW Voltage

(All outputs)

IOL = 8 mA (standard drive)

–

0.4

V

IOL = 12 mA (high drive)

–

0.4

V

VOH

Output HIGH Voltage

(All outputs)

IOH = –8 mA (standard drive)

2.4

–

V

IOH = –12 mA (high drive)

2.4

–

V

IDDPD

Power Down Supply Current

CLKIN=0 to VDD or floating (input

will be pulled-down by 250kΩ

weak pull-down on-chip resistor)

C-Grade

–

12

µA

I-Grade

–

25

µA

IDD1

Power Supply Current

All Outputs CL=0, 33MHz CLKIN

S2=S1=1 (High)

–

14

mA

IDD2

Power Supply Current

All Outputs CL=0, 66MHz CLKIN

S2=S1=1 (High)

–

26

mA

IDD3

Power Supply Current

All Outputs CL=0, 100MHz CLKIN

S2=S1=1 (High)

–

36

mA

IDD4

Power Supply Current

All Outputs CL=0, 133MHz CLKIN

S2=S1=1 (High)

–

44

mA

RPU/D

Pull-up and Pull-down Resistors

Pins-1/2/3/6/7/8/9/10/11/14/15/16

250kΩ-typ

175

325

kΩ

Symbol

Description

Condition

Min

Typ

Max

Unit

FMAX1

Maximum Frequency

[1]

(Input=Output )

All Active PLL Modes

High drive (-1H). All outputs CL=15pF

10

–

140

MHz

High drive (-1H), All outputs CL=30pF

10

–

100

MHz

Standard drive, (-1), All outputs CL=15pf

10

–

100

MHz

Standard drive, (-1), All outputs CL=30pf

10

–

66

MHz

FMAX2

Maximum Frequency

[1]

(Input=Output )

PLL Bypass Mode

(S2=1 and S1=0)

High drive (-1H). All outputs CL=15pF

0

–

140

MHz

High drive (-1H), All outputs CL=30pF

0

–

100

MHz

Standard drive, (-1), All outputs CL=15pf

0

–

100

MHz

Standard drive, (-1), All outputs CL=30pf

0

–

66

MHz

INDC

Input Duty Cycle

Measured at 1.4V, Fout=66MHz, CL=15pF

30

50

70

%

OUTDC1

Output Duty Cycle

[2]

Measured at 1.4V, Fout=66MHz, CL=15pF

40

50

60

%

OUTDC2

Output Duty Cycle

[2]

Measured at 1.4V, Fout=66MHz, CL=15pF

40

50

60

%

Not Recommended

for New Designs

SL2309SI-1HT

SL2309SI-1HT

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