ADA4858-3 Data Sheet
Rev. B | Page 16 of 20
PD (POWER-DOWN) PIN
The ADA4858-3 is equipped with a PD (power-down) pin for
all three amplifiers. This allows the user to reduce the quiescent
supply current when an amplifier is not active. The power-down
threshold levels are derived from ground level. The amplifiers are
powered down when the voltage applied to the PD pin is greater
than a certain voltage from ground. In a 5 V supply application, the
voltage is greater than 2 V, and in a 3.3 V supply application, the
voltage is greater than 1.5 V. The amplifier is enabled whenever the
PD pin is connected to ground. If the PD pin is not used, it is
best to connect it to ground. Note that the power-down feature
does not control the charge pump output voltage and current.
Table 6. Power-Down Voltage Control
PD Pin 5 V 3.3 V
Not active <1.5 V <1 V
Active >2 V >1.5 V
POWER SUPPLY BYPASSING
Careful attention must be paid to bypassing the power supply
pins of the ADA4858-3. High quality capacitors with low
equivalent series resistance (ESR), such as multilayer ceramic
capacitors (MLCCs), should be used to minimize supply
voltage ripple and power dissipation. A large, usually tantalum,
capacitor between 2.2 µF to 47 µF located in proximity to the
ADA4858-3 is required to provide good decoupling for lower
frequency signals. The actual value is determined by the circuit
transient and frequency requirements. In addition, place 0.1 µF
MLCC decoupling capacitors as close to each of the power
supply pins and across from both supplies as is physically
possible, no more than 1/8 inch away. The ground returns
should terminate immediately into the ground plane. Placing
the bypass capacitor return close to the load return minimizes
ground loops and improves performance.
LAYOUT
As is the case with all high speed applications, careful attention
to printed circuit board (PCB) layout details prevents associated
board parasitics from becoming problematic. The ADA4858-3 can
operate at up to 600 MHz; therefore, proper RF design techniques
must be employed. The PCB should have a ground plane covering
all unused portions of the component side of the board to provide a
low impedance return path. Removing the ground plane on all
layers from the area near and under the input and output pins
reduces stray capacitance. Keep signal lines connecting the
feedback and gain resistors as short as possible to minimize the
inductance and stray capacitance associated with these traces.
Place termination resistors and loads as close as possible to their
respective inputs and outputs. Keep input and output traces as
far apart as possible to minimize coupling (crosstalk) through the
board. Adherence to microstrip or stripline design techniques for
long signal traces (greater than 1 inch) is recommended. For
more information on high speed board layout, see “A Practical
Guide to High-Speed Printed-Circuit-Board Layout,” Analog
Dialogue, Volume 39, Number 3, September 2005.
