V
DD
V
SUPPLY
IN
CLK
GND
INPUT
OUTPUT
50k
50k
50k
OUT
0.1µF
0.1µF
0.1µF
CLOCK
SHDN
COM
OS
MAX7400
MAX7403
MAX7404
MAX7407
Figure 4. Offset Adjustment Circuit
MAX7400/MAX7403/MAX7404/MAX7407
8th-Order, Lowpass, Elliptic,
Switched-Capacitor Filters
10 ______________________________________________________________________________________
Clock Signal
External Clock
The MAX7400/MAX7403/MAX7404/MAX7407 SCFs
were designed for use with external clocks that have a
40% to 60% duty cycle. When using an external clock,
drive CLK with a CMOS gate powered from 0 to V
DD
.
Varying the rate of the external clock adjusts the filter
corner frequency:
f
C
= f
CLK
/ 100
Internal Clock
When using the internal oscillator, the capacitance
(C
OSC
) on the CLK pin determines the oscillator fre-
quency:
where K = 38 for the MAX7400/MAX7403, and K = 34
for the MAX7404/MAX7407. Since the capacitor value
is in picofarads, minimize the stray capacitance at CLK
so that it does not affect the internal oscillator frequen-
cy. Varying the rate of the internal oscillator adjusts the
filter’s corner frequency by a 100:1 clock-to-corner fre-
quency ratio. For example, an internal oscillator fre-
quency of 100kHz produces a nominal corner
frequency of 1kHz.
Input Impedance
vs. Clock Frequencies
The MAX7400/MAX7403/MAX7404/MAX7407’s input
impedance is effectively that of a switched-capacitor
resistor and is inversely proportional to frequency. The
input impedance determined by the following equation
represents the average input impedance, since the
input current is not continuous. As a rule, use a driver
with an output source impedance less than 10% of the
filter’s input impedance. Estimate the input impedance
of the filter using the following formula:
where f
CLK
= clock frequency and C
IN
= 0.85pF.
Low-Power Shutdown Mode
These devices feature a shutdown mode that is activat-
ed by driving SHDN low. Placing the filter in shutdown
mode reduces the supply current to 0.2µA (typ) and
places the output of the filter into a high-impedance
state. For normal operation, drive SHDN high or con-
nect to V
DD
.
Applications Information
Offset and Common-Mode
Input Adjustment
The voltage at COM sets the common-mode input volt-
age and is internally biased at midsupply by a resistor-
divider. Bypass COM with a 0.1µF capacitor and
connect OS to COM. For applications requiring offset
adjustment or DC level shifting, apply an external bias
voltage through a resistor-divider network to OS, as
shown in Figure 4. (Note: Do not leave OS unconnect-
ed.) The output voltage is represented by the following
equation:
V
OUT
= (V
IN
- V
COM
) + V
OS
Z
fC
IN
CLK IN
()
( )
Ω=
1
f (kHz) =
K 10
C
OSC
3
OSC
; CinpF
OSC
PASSBAND STOPBAND
GAIN (dB)
FREQUENCY
f
C
f
S
f
S
f
C
f
S
f
C
TRANSITION RATIO =
RIPPLE
Figure 3. Elliptic Filter Response
MAX7400/MAX7403/MAX7404/MAX7407
8th-Order, Lowpass, Elliptic,
Switched-Capacitor Filters
______________________________________________________________________________________ 11
with V
COM
= V
DD
/ 2 (typical), and where (V
IN
- V
COM
)
is lowpass filtered by the SCF, and V
OS
is added at the
output stage. See the
Electrical Characteristics
for
COM and OS input voltage ranges. Changing the volt-
age on COM or OS significantly from midsupply
reduces the filter’s dynamic range.
Power Supplies
The MAX7400/MAX7403 operate from a single +5V
supply. The MAX7404/MAX7407 operate from a single
+3V supply. Bypass V
DD
to GND with a 0.1µF capaci-
tor. If dual supplies are required, connect COM to the
system ground and GND to the negative supply. Figure
5 shows an example of dual-supply operation. Single-
supply and dual-supply performance are equivalent.
For single-supply or dual-supply operation, drive CLK
and SHDN from GND (V- in dual-supply operation) to
V
DD
. For a ±2.5V supply, use the MAX7400 or MAX7403;
for a ±1.5V supply, use MAX7404 or MAX7407. For ±5V
dual-supply applications, use the MAX291–MAX297.
Input Signal Amplitude Range
The ideal input signal range is determined by observ-
ing the voltage level at which the total harmonic
distortion plus noise (THD+N) is minimized for a given
corner frequency. The
Typical Operating Character-
istics
show THD+N response as the input signal’s
peak-to-peak amplitude is varied. These measurements
are made with OS and COM biased at midsupply.
Anti-Aliasing and Post-DAC Filtering
When using the MAX7400/MAX7403/MAX7404/
MAX7407 for anti-aliasing or post-DAC filtering, syn-
chronize the DAC and the filter clocks. If the clocks are
not synchronized, beat frequencies may alias into the
passband.
The high clock-to-corner frequency ratio (100:1) also
eases the requirements of pre- and post-SCF filtering.
At the input, a lowpass filter prevents the aliasing of fre-
quencies around the clock frequency into the pass-
band. At the output, a lowpass filter attenuates the
clock feedthrough.
A high clock-to-corner frequency ratio allows a simple
RC lowpass filter, with the cutoff frequency set above
the SCF corner frequency, to provide input anti-aliasing
and reasonable output clock attenuation.
Harmonic Distortion
Harmonic distortion arises from nonlinearities within the
filter. Such nonlinearities generate harmonics when a
pure sine wave is applied to the filter input. Table 1 lists
typical harmonic distortion values with a 10k load and
an input signal of 4Vp-p (MAX7400/MAX7403) or 2Vp-p
(MAX7404/MAX7407), at T
A
= +25°C.
V
DD
V+
V-
IN
CLK
GND
INPUT
OUTPUTOUT
0.1µF
CLOCK
*DRIVE SHDN TO V- FOR LOW-POWER SHUTDOWN MODE.
SHDN
COM
OS
0.1µF
MAX7400
MAX7403
MAX7404
MAX7407
*
V+
V-
Figure 5. Dual-Supply Operation
2nd
-88100
TYPICAL
HARMONIC
DISTORTION (dB)
1
f
C
(kHz)
-89100
200
1
-84
f
IN
(Hz)
200
4th3rd 5th
-89500
MAX7400
5 1000
-86-89-82
-88-93-77
500
MAX7403
5 1000
-87-91
FILTER
-81
-91-90-80
4
V
IN
(Vp-p)
4
f
CLK
(kHz)
-85100 1 200
-85500
MAX7404
5 1000
-86-85-82
-84-86-81
2
-85100 1 200
-86500
MAX7407
5 1000
-86-85-82
-86-85-84
2
Table 1. Typical Harmonic Distortion
MAX7400/MAX7403/MAX7404/MAX7407
8th-Order, Lowpass, Elliptic,
Switched-Capacitor Filters
Package Information
SOICN.EPS
TRANSISTOR COUNT: 1116
Ordering Information (continued) Chip Information
PART
MAX7403CSA
MAX7403CPA
MAX7403ESA -40°C to +85°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
8 SO
8 Plastic DIP
8 SO
MAX7403EPA -40°C to +85°C 8 Plastic DIP
MAX7404CSA
MAX7404CPA
MAX7404ESA -40°C to +85°C
0°C to +70°C
0°C to +70°C 8 SO
8 Plastic DIP
8 SO
MAX7404EPA -40°C to +85°C 8 Plastic DIP
MAX7407CSA
MAX7407CPA
MAX7407ESA -40°C to +85°C
0°C to +70°C
0°C to +70°C 8 SO
8 Plastic DIP
8 SO
MAX7407EPA -40°C to +85°C 8 Plastic DIP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

MAX7403ESA+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Active Filter 8th-Order Lowpass Elliptic Filter
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