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L6911CTR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Obsolete Product(s) - Obsolete Product(s)
L6911C
10/20
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the max-
imum input voltage available.
Output Capacitor
Since the microprocessors require a current variation beyond 10A doing load transients, with a slope in the
range of tenth A/
µ
sec, the output capacitor is a basic component for the fast response of the power supply. In
fact for first few microseconds they supply the current to the load. The controller recognizes immediately the
load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value.
The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):
∆
V
OUT
=
∆
I
OUT
· ESR
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
Where D
MAX
is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop
during load transient and the lower is the output voltage static ripple.
Input Capacitor
The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must
have a low ESR to minimize the losses. The rms value of this ripple is:
Where D is the duty cycle. The equation reaches its maximum value with D=0.5. The losses in worst case are:
Compensation network design
The control loop is a voltage mode (figure 7) that uses a droop function to satisfy the requirements for a VRM
module, reducing the size and the cost of the output capacitor.
This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de-
pendence of the output voltage on the load current: at light load the output voltage will be higher than the nom-
inal level, while at high load the output voltage will be lower than the nominal value.
t
application
L
∆
I
⋅
V
IN
V
OUT
–
------------------------------=
t
removal
L
∆
I
⋅
V
OUT
---------------=
∆
V
OUT
∆
I
OUT
2
L
2C
OUT
V
INMIN
D
MAX
V
OUT
–⋅()⋅⋅
---------------------------------------------------------------------------------------------=
I
rms
I
OUT
D1D
–()⋅=
P ESR I
rms
2
⋅=
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
11/20
L6911C
Figure 6. Output transient response without (a) and with (b) the droop function
As shown in figure 6, the ESR drop is present in any case, but using the droop function the total deviation of the
output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 6) propor-
tional to the output current. Since a sense resistor is not present, the output DC current is measured by using
the intrinsic resistance of the inductance (a few m
Ω
). So the low-pass filtered inductor voltage (that is the induc-
tor current) is added to the feedback signal, implementing the droop function in a simple way. Referring to the
schematic in figure 7, the static characteristic of the closed loop system is:
Where V
PROG
is the output voltage of the digital to analog converter (i.e. the set point) and R
L
is the inductance
resistance. The second term of the equation allows a positive offset at zero load (
∆
V
+
); the third term introduces
the droop effect (
∆
V
DROOP
). Note that the droop effect is equal the ESR drop if:
Figure 7. Compensation network
Considering the previous relationships R2, R3, R8 and R9 may be determined in order to obtain the desired
droop effect as follow:
■
Choose a value for R2 in the range of hundreds of K
Ω
to obtain realistic values for the other
components.
V
MAX
V
MIN
V
NOM
(a) (b)
ESR DROP ESR DROP
V
DROOP
V
OUT
V
PROG
V
PROG
R3 R8 // R9
+
R2
-------------------------------------
R
L
R8 // R9
⋅
R8
-----------------------------------
I
OUT
⋅–⋅+=
R
L
R8 // R9
⋅
R8
-----------------------------------
ESR
=
C18
C20 R4
R3
R9
L2
ESR
C6-15
R8
R2
PWM
C25
V
IN
V
PROG
R
L
Z
F
Z
I
V
OUT
V
PHASE
V
COMP
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
L6911C
12/20
■
From the above equations, it results:
;
;
Where I
MAX
is the maximum output current.
■
The component R3 must be chosen in order to obtain R3<<R8//R9 to permit these and successive
simplifications.
Therefore, with the droop function the output voltage decreases as the load current increases, so the DC output
impedance is equal to a resistance R
OUT
. It is easy to verify that the output voltage deviation under load tran-
sient is minimum when the output impedance is constant with frequency.
To choose the other components of the compensation network, the transfer function of the voltage loop is con-
sidered. To simplify the analysis is supposed that R3 << Rd, where Rd = (R8//R9).
Figure 8. Compensation network definition
The transfer function may be evaluated neglecting the connection of R8 to PHASE because, as will see later,
this connection is important only at low frequencies. So R4 is considered connected to VOUT. Under this as-
sumption, the voltage loop has the following transfer function:
R8
∆
V
+
R2
⋅
V
PROG
-----------------------
R
L
I
MAX
⋅
V
DROOP
∆
---------------------------
⋅=
R9 R8
=
V
DROOP
∆
R
L
I
MAX
⋅
---------------------------
1
1
V
DROOP
∆
R
L
I
MAX
⋅
---------------------------+
-------------------------------------
⋅⋅
|Av|
|R|
|G loop|
f
f
f
fc
f
D
f
2
f
1
f
3
R
0
2
f
LC
f
CE
f
EC
f
CC
G
0
acitorCeramicCapCceramicRceramic
CC
f
byIntroducedCceramicESR
EC
f
ESRzero
OUT
CESR
CE
f
doublepoleLC
LC
fingularityConverterS
⋅⋅=
⋅⋅=
⋅⋅=
⋅=
π
π
π
π
2/1
2/1
2/1
2/1
252/1
2532/1
3
20)43(2/1
2
2042/1
1
CRd
d
f
CRf
CRRf
CRfingularityonNetworkSCompensati
⋅⋅=
⋅⋅=
⋅+⋅=
⋅⋅=
π
π
π
π
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L6911CTR

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Manufacturer:
STMicroelectronics
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IC REG CTRLR BUCK 20SOIC
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