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AS7C3256A-12TIN

P1-P3P4-P6P7-P9
®
AS7C3256A
4/23/04; v.2.0 Alliance Semiconductor P. 4 of 9
Read cycle (over the operating range)
3,9
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read waveform 2 (CE controlled)
3,6,8,9
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time t
RC
10–12–15–20–ns
Address access time t
AA
– 10 – 12 – 15 – 20 ns 3
Chip enable (CE
) access time
t
ACE
– 10 – 12 – 15 – 20 ns 3
Output enable (OE
) access time
t
OE
–5–6–7–8ns
Output hold from address change t
OH
3–3–3–3–ns5
CE
LOW to output in low Z
t
CLZ
3–3–3–3–ns4, 5
CE
HIGH to output in high Z
t
CHZ
–3–3–4–5ns4, 5
OE
LOW to output in low Z
t
OLZ
0–0–0–0–ns4, 5
OE
HIGH to output in high Z
t
OHZ
–3–3–4–5ns4, 5
Power up time t
PU
0–0–0–0–ns4, 5
Power down time t
PD
– 10 – 12 – 15 – 20 ns 4, 5
Undefined output/don’t careFalling inputRising input
Address
D
out
Data valid
t
OH
t
AA
t
RC
Supply
current
CE
OE
D
out
t
RC
1
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
t
OHZ
Data valid
AS7C3256A
4/23/04; v.2.0 Alliance Semiconductor P. 5 of 9
®
Write cycle (over the operating range)
11
Write waveform 1 (WE controlled)
10,11
Write waveform 2 (CE controlled)
10,11
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time t
WC
10–12–15–20–ns
Chip enable to write end t
CW
8 – 8 –10–12–ns
Address setup to write end t
AW
8 – 8 –10–12–ns
Address setup time t
AS
0–0–0–0–ns
Write pulse width t
WP
7–8–9–12–ns
Write recovery time t
WR
0–0–0–0–ns
Address hold from end of write t
AH
0–0–0–0–ns
Data valid to write end t
DW
5–6–8–10–ns
Data hold time t
DH
0–0–0–0–ns4, 5
Write enable to output in high Z t
WZ
–5–6–7–8ns4, 5
Output active from write end t
OW
3–3–3–3–ns4, 5
t
AW
t
AH
t
WC
Address
WE
D
in
D
out
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
t
WR
t
AW
Address
CE
WE
D
in
D
out
Data valid
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
t
WR
®
AS7C3256A
4/23/04; v.2.0 Alliance Semiconductor P. 6 of 9
AC test conditions
Notes
1During V
CC
power-up, a pull-up resistor to V
CC
on
CE
is required to meet I
SB
specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B.
4 These parameters are specified with CL = 5pF, as in Figures B. Transition is measured
±500mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6
WE
is High for read cycle.
7
CE
and
OE
are Low for read cycle.
8 Address valid prior to or coincident with
CE
transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.
350
Ω
C
13
320
Ω
D
out
GND
+3.3V
168
Ω
D
out
+1.72V
Figure B: Output load
Thevenin equivalent
- Output
l
oa
d
: see F
i
gure B
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
P1-P3P4-P6P7-P9

AS7C3256A-12TIN

Mfr. #:
Buy AS7C3256A-12TIN
Manufacturer:
Alliance Memory
Description:
SRAM 256K 3.3V 12ns FAST 32K x 8 Asynch SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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