Technical Note
4/15
www.rohm.com
2011.02 - Rev.
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BD9328EFJ
●Block Operation
・VREG
A block to generate constant-voltage for DC/DC boosting.
・VREF
A block that generates internal reference voltage of 5.1 V (Typ.).
・TSD/UVLO
TSD (Thermal shutdown)/UVLO (Under Voltage Lockout) protection block.
The TSD circuit shuts down IC at high temperature.
The UVLO circuit shuts down the IC when the VCC is Low Voltage.
・Error amp block (ERR)
This is the circuit to compare the reference voltage and the feedback voltage of output voltage. The COMP pin voltage
resulting from this comparison determines the switching duty. At the time of startup, since the soft start is operated by
the SS pin voltage, the COMP pin voltage is limited to the SS pin voltage.
・Oscillator block (OSC)
This block generates the oscillating frequency.
・SLOPE block
This block generates the triangular waveform from the clock created by OSC. Generated triangular waveform is sent to
the PWM comparator.
・PWM block
The COMP pin voltage output by the error amp is compared to the SLOPE block's triangular waveform to determine the
switching duty. Since the switching duty is limited by the maximum duty ratio which is determined internally, it does not
become 100%.
・DRV block
A DC/DC driver block. A signal from the PWM is input to drive the power FETs.
・Soft start circuit
Since the output voltage rises gradually while restricting the current at the time of startup, it is possible to prevent the
output voltage overshoot or the rush current.
