© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 7
1 Publication Order Number:
MC100EP14/D
MC100EP14
3.3V / 5V 1:5 Differential
ECL/PECL/HSTL Clock Driver
Description
The MC100EP14 is a low skew 1−to−5 differential driver, designed with
clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single−ended (if the V
BB
output is used). HSTL inputs can be used when
the LVEP14 is operating under PECL conditions.
The EP14 specifically guarantees low output−to−output skew. Optimal
design, layout, and processing minimize skew within a device and from
device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated even if only one output is
being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN
) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
• 400 ps Typical Propagation Delay
• 100 ps Device−to−Device Skew
• 25 ps Within Device Skew
• Maximum Frequency > 2 GHz Typical
• The 100 Series Contains Temperature Compensation
• PECL and HSTL Mode:
V
CC
= 3.0 V to 5.5 V with V
EE
= 0 V
• NECL Mode:
V
CC
= 0 V with V
EE
= −3.0 V to −5.5 V
• Open Input Default State
• These are Pb−Free Devices
TSSOP−20
DT SUFFIX
CASE 948E
MARKING DIAGRAM*
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
http://onsemi.com
100
EP14
ALYWG
G
1
20
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
