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DC and AC parameters M41T00SC64
14/19
Table 8. AC characteristics (serial EEPROM, M24C64)
Symbol Alt. Parameter
Test
condition
Min. Max. Unit
f
C
f
SCL
Clock frequency 400 kHz
t
CHCL
t
HIGH
Clock pulse width high 600 ns
t
CLCH
t
LOW
Clock pulse width low 1300 ns
t
DL1DL2
(1)
1. Sampled only, not 100% tested.
t
F
SDA fall time 20 300 ns
t
DXCX
t
SU:DAT
Data in set up time 100 ns
t
CLDX
t
HD:DAT
Data in hold time 0 ns
t
CLQX
t
DH
Data out hold time 200 ns
t
CLQV
(2)
2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the
falling or rising edge of SDA
t
AA
Clock low to next data valid
(access time)
200 900 ns
t
CHDX
(3)
3. For a reSTART condition, or following a Write cycle.
t
SU:STA
Start condition set up time 600 ns
t
DLCL
t
HD:STA
Start condition hold time 600 ns
t
CHDH
t
SU:STO
Stop condition set up time 600 ns
t
DHDL
t
BUF
Time between stop condition and next
start condition
1300 ns
t
W
t
WR
Write time 5 ms
t
NS
Pulse width ignored (input filter on SCL
and SDA for serial EEPROM)
Single
glitch
200 ns
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