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9DB108BFLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
10
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
0723G—12/02/08
SMBus Table: DEVICE ID
Pin # Name Control Function Type 0 1 PWD
Bit 7 RW 0
Bit 6 RW 0
Bit 5 RW 0
Bit 4 RW 0
Bit 3 RW 1
Bit 2 RW 0
Bit 1 RW 0
Bit 0 RW 0
SMBus Table: Byte Count Register
Pin # Name
Control
Function
Type 0 1 PWD
Bit 7 BC7 RW - - 0
Bit 6 BC6 RW - - 0
Bit 5 BC5 RW - - 0
Bit 4 BC4 RW - - 0
Bit 3 BC3 RW - - 0
Bit 2 BC2 RW - - 1
Bit 1 BC1 RW - - 0
Bit 0 BC0 RW - - 1
-
-
-
-
-
Byte 5
-
-
-
Byte 6
-
Writing to this
register configures
how many bytes
will be read back.
-
-
-
-
-
-
-
Device ID 6 Reserved
Device ID 7 (MSB) Reserved
Device ID 5 Reserved
Device ID 4 Reserved
Device ID 3 Reserved
Device ID 0 Reserved
Device ID 2 Reserved
Device ID 1 Reserved
11
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
0723G—12/02/08
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before
shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering
down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending
on the PD# drive mode and Output control bits) before the PLL is shut down.
PD#, Power Down
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x I
REF
and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PD# Assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion.
PD# De-assertion
PWRDWN#
DIF
DIF#
PWRDWN#
DIF
DIF#
Tstable
<1mS
Tdrive_PwrDwn#
<300uS, >200mV
12
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
0723G—12/02/08
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xI
REF.
DIF# is not driven, but pulled low by the termination. When the
SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
SRC_STOP# - Assertion
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
SRC_STOP# - De-assertion (transition from '0' to '1')
The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
SRC_STOP#
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

9DB108BFLF

Mfr. #:
Buy 9DB108BFLF
Manufacturer:
IDT
Description:
Clock Buffer PCIE BUFFER
Lifecycle:
New from this manufacturer.
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