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AD7151BRMZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
AD7151
Rev. 0 | Page 6 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
G
ND
1
VDD
2
NC
3
CIN
4
NC
NC = NO CONNECT
5
SDA
10
SCL
9
NC
8
OUT
7
EXC
6
AD7151
TOP VIEW
(Not to Scale)
07086-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 GND Ground Pin.
2 VDD
Power Supply Voltage. This pin should be decoupled to GND using a low impedance capacitor, for example,
0.1 μF X7R multilayer ceramic.
3 NC This pin should be left as an open circuit or connected to GND.
4 CIN CDC Capacitive Input. The measured capacitance (sensor) is connected between the EXC pin and the CIN pin.
5 NC This pin should be left as an open circuit.
6 EXC CDC Excitation Output. The measured capacitance is connected between the EXC pin and the CIN pin.
7 OUT Logic Output. High level on this output indicates proximity detected on the capacitive input.
8 NC This pin should be left as an open circuit.
9 SCL
Serial Interface Clock Input. Connects to the master clock line. Requires a pull-up resistor if not provided
elsewhere in the system.
10 SDA
Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided
elsewhere in the system.
AD7151
Rev. 0 | Page 7 of 28
25020015010050
OFFSET ERROR (fF)
CAPACITANCE CIN TO GND (pF)
TYPICAL PERFORMANCE CHARACTERISTICS
300
200
100
0
–100
03
00
07086-104
25020015010050
GAIN ERROR (%FS)
CAPACITANCE CIN TO GND (pF)
Figure 4. Capacitance Input Offset Error vs. Capacitance CIN to GND,
V
DD
= 3.3 V, EXC Pin Open Circuit
2
–8
–6
–4
–2
0
03
00
07086-105
25020015010050
OFFSET ERROR (fF)
CAPACITANCE EXC TO GND (pF)
Figure 5. Capacitance Input Gain Error vs. Capacitance CIN to GND,
V
DD
= 3.3 V, CIN to EXC = 2 pF
2
–2
–1
0
1
03
00
07086-106
0.10
–0.10
–0.05
0
0.05
030025020015010050
GAIN ERROR (%FS)
CAPACITANCE EXC TO GND (pF)
07086-107
Figure 6. Capacitance Input Offset Error vs. Capacitance EXC to GND,
V
DD
= 3.3 V, CIN Pin Open Circuit
Figure 7. Capacitance Input Gain Error vs. Capacitance EXC to GND,
V
DD
= 3.3 V, CIN to EXC = 2 pF
200
–200
–100
0
100
1100010010
OFFSET ERROR (fF)
RESISTANCE CIN TO GND (MΩ)
07086-108
Figure 8. Capacitance Input Offset Error vs. Resistance CIN to GND,
V
DD
= 3.3 V, EXC Pin Open Circuit
10
–10
–5
0
5
1100010010
GAIN ERROR (%FS)
RESISTANCE CIN TO GND (MΩ)
07086-109
Figure 9. Capacitance Input Gain Error vs. Resistance CIN to GND,
V
DD
= 3.3 V, CIN to EXC = 2 pF
AD7151
Rev. 0 | Page 8 of 28
8642
OFFSET ERROR (fF)
RESISTANCE EXC TO GND (MΩ)
10
–10
–5
0
5
01
0
10
–10
–5
0
5
1100010010
GAIN ERROR (%FS)
PARALLEL RESISTANCE (MΩ)
07086-110
8642
GAIN ERROR (%FS)
RESISTANCE EXC TO GND (MΩ)
Figure 10. Capacitance Input Offset Error vs. Resistance EXC to GND,
V
DD
= 3.3 V, CIN Pin Open Circuit
0.50
–0.50
–0.25
0
0.25
01
0
07086-113
4
–4
–2
0
2
–50 1007550250–25
OFFSET ERROR (fF)
TEMPERATURE (°C)
07086-111
20015010050
GAIN ERROR (%FS)
SERIAL RESISTANCE (kΩ)
Figure 11. Capacitance Input Gain Error vs. Resistance EXC to GND,
V
DD
= 3.3 V, CIN to EXC = 2 pF
2
–2
–1
0
1
02
50
07086-112
Figure 12. Capacitance Input Gain Error vs. Serial Resistance
V
DD
= 3.3 V, CIN to EXC = 2 pF
Figure 13. Capacitance Input Gain Error vs. Parallel Resistance,
V
DD
= 3.3 V, CIN to EXC = 2 pF
07086-114
0.2
–0.2
–0.2
–0.1
0
0.1
–50 1007550250–25
GAIN ERROR (%FS)
TEMPERATURE (°C)
Figure 14. Capacitance Input Offset Error vs. Temperature,
V
DD
= 3.3 V, CIN and EXC Pins Open Circuit
07086-115
Figure 15. Capacitance Input Gain Error vs. Temperature,
V
DD
= 3.3 V, CIN to EXC = 2 pF
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AD7151BRMZ

Mfr. #:
Buy AD7151BRMZ
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 1-CH Cap Proximity Sensor Inter IC
Lifecycle:
New from this manufacturer.
Delivery:
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