6
Notes:
1. Derate linearly above 85°C free-air temperature at a rate of 0.25 mA/°C.
2. Derate linearly above 85°C free-air temperature at a rate of 0.30 mA/°C.
3. Derate linearly above 85°C free-air temperature at a rate of 0.375 mW/°C.
4. Derate linearly above 85°C free-air temperature at a rate of 1.875 mW/°C.
5. CURRENT TRANSFER RATIO in percent is dened as the ratio of output collector current, I
O
, to the forward LED input current, I
F
, times 100.
6. Device considered a two terminal device: pin 1 and 3 shorted together and pins 4, 5 and 6 shorted together.
7. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
RMS
for 1 second (leakage detection
current limit, II-O ≤ 5 μA).
8. Common transient immunity in a Logic High level is the maximum tolerable (positive) dV
CM
/dt on the rising edge of the common mode pulse, V
CM
,
to assure that the output will remain in a Logic High state (i.e., V
O
> 2.0 V). Common mode transient immunity in a Logic Low level is the maximum
tolerable (negative) dV
CM
/dt on the falling edge of the common mode pulse signal, V
CM
to assure that the output will remain in a Logic Low state
(i.e., V
O
< 0.8 V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 k pull-up resistor.
10. The frequency at which the ac output voltage is 3 dB below its mid-frequency value.
11. Use of a 0.1 μF bypass capacitor connected between pins 4 and 6 is recommended.
12. Pulse Width Distortion (PWD) is dened as |t
PHL
- t
PLH
| for any given device.
13. The dierence between t
PLH
and t
PHL
between any two parts under the same test condition. In accordance with UL1577, each optocoupler is proof
tested by applying an insulation test voltage ≥ 4500 V
RMS
for 1 second (leakage detection current limit, II-O ≤ 5 μA).
14. Pulse: f = 0 kHz, Duty Cycle = 10%.
15. Use of a 0.1 μF bypass capacitor connected between pins 4 and 6 can improve performance by ltering power supply line noise.
16. The dierence between t
PLH
and t
PHL
between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay
Specications section.)
17. Common mode transient immunity in a Logic High level is the maximum tolerable dV
CM
/dt of the common mode pulse, VCM, to assure that the
output will remain in a Logic High state (i.e., V
O
> 3.0 V).
18. Common mode transient immunity in a Logic Low level is the maximum tolerable dV
CM
/dt of the common mode pulse, VCM, to assure that the
output will remain in a Logic Low state (i.e., V
O
< 1.0 V).
19. Pulse Width Distortion (PWD) is dened as |t
PHL
- t
PLH
| for any given device.
Switching Specications
Over recommended operating (T
A
= -40°C to 125°C), I
F
= 10mA, V
CC
= 5.0 V unless otherwise specied.
Parameter Symbol Min Typ Max Units Test Conditions Fig. Note
Propagation Delay
Time to Logic Low
at Output
T
PHL
0.08 0.20 0.80 ms T
A
=25°C Pulse: f = 10kHz, Duty cycle
= 50%, I
F
= 10mA, V
CC
= 5.0
V, R
L
= 1.9kW,C
L
= 15pF V
THHL
= 1.5V
5,6,
8
9
0.06 1.00 ms
Propagation Delay
Time to Logic High
at Output
T
PLH
0.15 0.30 0.80 ms T
A
=25°C Pulse: f = 10kHz, Duty cycle =
50%, I
F
= 10mA, V
CC
= 5.0 V,
R
L
= 1.9kW C
L
= 15pF V
THLH
= 2.0V
5,6,
8
9
0.03 1.00 ms
Pulse Width
Distortion
PWD 0 0.40 0. 45 ms T
A
=25°C Pulse: f=10kHz, Duty cycle
=50%, I
F
= 10mA, V
CC
= 5.0V,
R
L
= 1.9kW, C
L
= 15pF, V
THHL
=
1.5V, V
THLH
= 2.0V
12
0 0.85 ms
Propagation Delay
Dierence Between
Any 2 Parts
t
PLH-tPHL
0 0.40 0.50 ms T
A
=25°C Pulse: f = 10kHz, Duty cycle
= 50%, I
F
= 10mA, V
CC
= 5.0V,
R
L
= 1.9kW, C
L
= 15pF, V
THHL
=
1.5V, V
THLH
= 2.0V
13
0 0.90 ms
Common Mode
Transient Immu-
nity at Logic High
Output
|CM
H
| 15 30 kV/ms V
CM
= 1500Vp-p, I
F
= 0mA, T
A
= 25°C, R = 1.9kW
9 8, 9
Common Mode
Transient Immunity
at Logic Low Output
|CM
L
| 15 30 kV/ms V
CM
= 1500Vp-p, I
F
= 10mA,
T
A
= 25°C, R
L
= 1.9kW
