LTC4305
4305f
4
The denotes specifications which apply over the full specified temperature
range, otherwise specifications are at T
A
= 25°C. V
CC
= 3.3V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Guaranteed by design and not subject to test, unless stated
otherwise in the Conditions.
Note 3: The boosted pull-up currents are regulated to prevent excessively
fast edges for light loads. See the Typical Performance Characteristics for
rise time as a function of V
CC
and parasitic bus capacitance C
BUS
and for
I
BOOST
as a function of V
CC
and temperature.
Note 4: When a logic low voltage V
LOW
is forced on one side of the
upstream-downstream buffers, the voltage on the other side is regulated
to a voltage V
LOW2
= V
LOW
+ V
OS
is a positive offset voltage. V
OS,DOWN-BUF
is the offset voltage when the LTC4305 is driving the upstream pin (e.g.,
SDAIN) and V
OS,DOWN-BUF
is the offset voltage when the LTC4305 is
driving the downstream pin (e.g., SDA1). See the Typical Performance
Characteristics for V
OS,UP-BUF
and V
OS,DOWN-BUF
as a function of V
CC
and
bus pull-up current.
Note 5: When floating, the ADR0–ADR2 pins can tolerate pin leakage
currents up to I
ADR,FLOAT
and still convert the address correctly.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
2
C Interface
V
ADR(H)
ADR0–2 Input High Voltage 0.75 V
CC
0.9 V
CC
V
V
ADR(L)
ADR0–2 Input Low Voltage 0.1 V
CC
0.25 V
CC
V
I
ADR(IN, L)
ADR0–2 Logic Low Input Current ADR0–2 = 0V, V
CC
= 5.5V –30 –60 –80 µA
I
ADR(IN, H)
ADR0–2 Logic High Input Current ADR0–2 = V
CC
= 5.5V 30 60 80 µA
I
ADR,FLOAT
ADR0–2 Allowed Input Current V
CC
= 2.7V, 5.5V (Note 5) ±5 ±13 µA
V
SDAIN,SCLIN(TH)
SDAIN, SCLIN Input Falling Threshold Voltages V
CC
= 5.5V 1.4 1.6 1.8 V
V
SDAIN,SCLIN(HY)
SDAIN, SCLIN Hysteresis 30 mV
I
SDAIN,SCLIN(OH)
SDAIN, SCLIN Input Current SCL, SDA = V
CC
±
5 µA
C
IN
SDA, SCL Input Capacitance (Note 2) 6 10 pF
V
SDAIN(OL)
SDAIN Output Low Voltage I
SDA
= 4mA, V
CC
= 2.7V 0.2 0.4 V
I
2
C Interface Timing
f
SCL
Maximum SCL Clock Frequency (Note 2) 400 kHz
t
BUF
Bus Free Time Between Stop/Start Condition (Note 2) 0.75 1.3 µs
t
HD, STA
Hold Time After (Repeated) Start Condition (Note 2) 45 100 ns
t
SU, STA
Repeated Start Condition Set-Up Time (Note 2) –30 0 ns
t
SU, STO
Stop Condition Set-Up Time (Note 2) –30 0 ns
t
HD, DATI
Data Hold Time Input (Note 2) –25 0 ns
t
HD, DATO
Data Hold Time Output (Note 2) 300 600 900 ns
t
SU, DAT
Data Set-Up Time (Note 2) 50 100 ns
t
f
SCL, SDA Fall Times (Note 2) 20 + 0.1 300 ns
C
BUS
t
SP
Pulse Width of Spikes Suppressed by the (Note 2) 50 150 250 ns
Input Filter
LTC4305
5
4305f
CAPACITANCE, C
BUS
(pF)
0
RISE TIME (ns)
150
200
250
800
4305 G02
100
50
0
200
400
600
1000
V
CC
= 3.3V
V
CC
= 5V
dV = 0.3V • V
CC
TO 0.7V • V
CC
R
BUS
= 10k
TEMPERATURE (°C)
–50
t
PHL
(ns)
80
100
120
25 75
4305 G01
60
40
–25 0
50 100 125
20
0
V
CC
= 3.3V
V
CC
= 5V
TEMPERATURE (°C)
–50
CURRENT (mA)
4
5
6
25 75
4305 G03
3
2
–25 0
50 100 125
1
0
V
CC
= 3.3V
V
CC
= 5V
UPSTREAM CONNECTED TO CHANNEL 1,
SCL BUS LOW, SDA BUS HIGH
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Rise Time vs C
BUS
vs V
CC
Buffer Circuitry t
PHL
vs Temperature I
CC
vs Temperature
V
OS,DOWN-BUF
vs Bus Pull-Up CurrentV
OS,UP-BUF
vs Bus Pull-Up Current
I
BOOST
vs Temperature
BUS PULL-UP CURRENT (mA)
10
V
OS
(mV)
100
120
140
4305 G04
80
60
0
2
3
4
40
20
180
160
V
CC
= 3.3V
V
CC
= 5V
BUS PULL-UP CURRENT (mA)
0
0
V
OS
(mV)
50
100
150
200
250
300
12 34
4305 G05
V
CC
= 3.3V
V
CC
= 5V
(T
A
= 25°C unless otherwise specified.)
Downstream R
FET
on Resistance
vs V
CC
and Temperature
TEMPERATURE (°C)
–50
0
R
ON
()
5
15
20
25
50
45
4305 G06
10
0
–25
75 100
25 125
30
35
40
V
CC
= 3.3V
V
CC
= 5V
TEMPERATURE (°C)
–50 25 75–25 0 50 100 125
I
BOOST
(mA)
10
12
4305 G07
8
6
0
4
2
14
V
CC
= 3.3V
V
CC
= 5V
LTC4305
4305f
6
ALERT1–ALERT2 (Pins 14, 1): Fault Alert Inputs,
Channels 1–2. Devices on each of the two output channels
can pull their respective pin low to indicate that a fault has
occurred. The LTC4305 then pulls the ALERT low to pass
the fault indication on to the host. See the “Operation”
section below for the details of how ALERT is set and
cleared. Connect unused fault alert inputs to V
CC
.
ALERT (Pin 2): Fault Alert Output. An open-drain output
that is pulled low when a fault occurs to alert the host
controller. The LTC4305 pulls ALERT low when any of the
ALERT1–ALERT2 pins is low; when the two-wire bus is
stuck low; or when the Connection Requirement bit of
register 2 is low and a master tries to connect to a
downstream channel that is low. See the “Operation”
section below for the details of how ALERT is set and
cleared. The LTC4305 is compatible with the SMBus Alert
Response Address protocol. Connect a 10k resistor to a
power supply voltage to provide the pull-up. Tie to ground
if unused.
SDAIN (Pin 3): Serial Bus Data Input and Output. Connect
this pin to the SDA line on the master side. An external
pull-up resistor or current source is required.
GND (Pin 4): Device Ground.
SCLIN (Pin 5): Serial Bus Clock Input. Connect this pin to
the SCL line on the master side. An external pull-up
resistor or current source is required.
ENABLE (Pin 6): Digital Interface Enable and Register
Reset. Driving ENABLE high enables I
2
C communication
to the LTC4305. Driving ENABLE low disables I
2
C com-
munication to the LTC4305 and resets the registers to
their default state as shown in the Operations section.
When ENABLE returns high, masters can read and write
the LTC4305 again. If unused, tie ENABLE to V
CC
.
V
CC
(Pin 7): Power Supply Voltage. Connect a bypass
capacitor of at least 0.01µF directly between V
CC
and GND
for best results.
ADR0–ADR2 (Pins 8–10): Three-State Serial Bus
Address Inputs. Each pin may be floated, tied to ground,
or tied to V
CC
. There are therefore 27 possible addresses.
See Table 1 in Applications Information section. When the
pins are floated, they can tolerate ±5µA of leakage current
and still convert the address correctly.
READY (Pin 11): Connection Ready Digital Output. An
N-channel MOSFET open-drain output transistor that pulls
down when none of the downstream channels is con-
nected to the upstream bus and turns off when one or
more downstream channels is connected to the upstream
bus. Connect a 10k resistor to a power supply voltage to
provide the pull-up. Tie to ground if unused.
SCL1–SCL2 (Pins 12, 16): Serial Bus Clock Outputs
Channels 1–2. Connect pins SCL1–SCL2 to the SCL lines
on the downstream channels 1–2, respectively. It is ac-
ceptable to float any pin that will never be connected to the
upstream bus. Otherwise, an external pull-up resistor or
current source is required on each pin.
SDA1–SDA2 (Pins 13, 15): Serial Bus Data Output
Channels 1–2. Connect pins SDA1–SDA2 to the SDA lines on
downstream channels 1–2, respectively. It is acceptable
to float any pin that will never be connected to the
upstream bus. Otherwise, an external pull-up resistor or
current source is required on each pin.
Exposed Pad (Pin 17, DHD Package Only): Exposed pad
may be left open or connected to device ground.
UU
U
PI FU CTIO S

LTC4305CDHD#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 2:1 I2C MUX and Bus Buffer
Lifecycle:
New from this manufacturer.
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