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AD1877JRZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD1877
REV. A
–15–
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
32 1 2 16 17 18 19 1 2 16 17 18 19 20 1 2
MSB-14 LSB
PREVIOUS DATA
MSB-1
LEFT DATA
MSB-2
LSB
RIGHT DATA
SOUT
OUTPUT
ZEROS ZEROS
MSB-1 MSB-2
LSB
ZEROS
WCLK
OUTPUT
TAG
OUTPUT
MSB LSB
LEFT TAG
MSB LSB
RIGHT TAG
20
LRCK
OUTPUT
OUTPUT
MSB MSB
Figure 12. Serial Data Output Timing. Master Mode, Right-Justified with MSB Delay,
WCLK Pulsed in 17th BCLK Cycle, S/
M
= LO, R
L
JUST = Hl,
MSBDLY
= LO
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
31 32 1 2 3 16
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
LSB
LEFT TAG
LSB
RIGHT TAG
31 32 1 2 3 16
MSB-1
LEFT DATA
MSB-2
LSB
MSB-1
RIGHT DATA
MSB-2
LSB
ZEROSZEROS ZEROS
LRCK
OUTPUT
OUTPUT 17 1817 18
MSB
MSB
MSB
MSB
Figure 13. Serial Data Output Timing: Master Mode, Left-Justified with No MSB Delay,
S/
M
= LO, R
L
JUST = LO,
MSBDLY
= Hl
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
321234 17
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
MSB
LEFT TAG
MSB
RIGHT TAG
31 32 1 2 3 4 17
MSB-1
LEFT DATA
MSB-2
LSB
MSB-1
RIGHT DATA
MSB-2
LSB
ZEROSZEROS ZEROS
OUTPUT
LRCK
OUTPUT
MSB
LSB
MSB
LSB
Figure 14. Serial Data Output Timing: Master Mode, I
2
S-Justified, S/
M
= LO, R
L
JUST = LO,
MSBDLY
= LO
AD1877
REV. A
–16–
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
31 32 1 2 3 4 16
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
19 20 21 32 1 2
INPUT
HI HI
51718
LSB
LEFT TAG
MSB LSB
RIGHT TAG LEFT TAG
LSB
MSB-14
LSB
PREVIOUS DATA
MSB-1 MSB-2 MSB-3
LEFT DATA
MSB-4 MSB-3 MSB-4
LSB
MSB-1 MSB-2
RIGHT DATA
LSB
MSB-1
LEFT DATA
LRCK
INPUT
MSB
MSB
MSB MSB
MSB
Figure 15. Serial Data Output Timing: Slave Mode, Left-Justified with No MSB Delay,
32-Bit Frame Mode, S/
M
= Hl, R
L
JUST = LO,
MSBDLY
= Hl
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
32 1 2 3 4 5 17
SOUT
OUTPUT
TAG
OUTPUT
20 21 22 1 2 3
INPUT
WCLK
OUTPUT
HI HI
61819
MSB
LEFT TAG
MSB LSB
RIGHT TAG
MSB-14
LSB
PREVIOUS DATA
MSB-1 MSB-2 MSB-3
LEFT DATA
MSB-4 MSB-3 MSB-4
LSB
MSB-1 MSB-2
RIGHT DATA
LSB
MSB-1
LEFT DATA
MSB
LEFT TAG
MSB
RIGHT TAG
LRCK
INPUT
MSB
LSB
MSB MSB
LSB
Figure 16. Serial Data Output Timing: Slave Mode, I
2
S-Justified, 32-Bit Frame Mode,
S/
M
= Hl, R
L
JUST= LO,
MSBDLY
= LO
BCLK OUTPUT (64 x F
S
)
RDEDGE = LO
CLKIN
INPUT
BCLK OUTPUT (64 x F
S
)
RDEDGE = HI
WCLK
OUTPUT
DATA & TAG
OUTPUTS
XMIT XMITXMIT XMIT
t
DLYCKB
t
BPWL
t
BPWH
t
BPWL
t
BPWH
t
DLYBLR
t
DLYDT
t
DLYBWR
t
DLYBWF
LRCK
OUTPUT
Figure 17. Master Mode Clock Timing
AD1877
REV. A
–17–
WCLK
INPUT
DATA & TAG
OUTPUTS
XMIT SAMPLE SAMPLE
t
BPWL
t
BPWH
t
BPWH
t
BPWL
t
DLYLRDT
MSB MSB-1
t
DLYBDT
t
SETLRBS
BCLK INPUT
RDEDGE = LO
BCLK OUTPUT
RDEDGE = HI
LRCK
INPUT
XMIT
t
SETWBS
Figure 18. Slave Mode Clock Timing
CLKIN INPUT
RESET INPUT
t
CPWH
t
CPWL
t
CLKIN
t
RPWL
Figure 19. CLKIN and
RESET
Timing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD1877JRZ

Mfr. #:
Buy AD1877JRZ
Manufacturer:
Analog Devices Inc.
Description:
Audio A/D Converter ICs IC 16-Bit Stereo
Lifecycle:
New from this manufacturer.
Delivery:
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