10
FN7104.7
August 10, 2007
output to eliminate most peaking. However, this will reduce
the gain slightly. If the gain setting is greater than 1, the gain
resistor R
G
can then be chosen to make up for any gain loss
which may be created by the additional series resistor at the
output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier’s output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL8102 can be disabled and its output placed in a high
impedance state. The turn-off time is about 25ns and the
turn-on time is about 200ns. When disabled, the amplifiers
supply current is reduced to 30µA typically, thereby
effectively eliminating the power consumption. The
amplifier’s power down can be controlled by standard TTL or
CMOS signal levels at the ENABLE
pin. The applied logic
signal is relative to V
S
- pin. Letting the ENABLE pin float or
applying a signal that is less than 0.8V above V
S
- will enable
the amplifier. The amplifier will be disabled when the signal
at ENABLE
pin is 2V above V
S
-.
Output Drive Capability
The EL8102, EL8103 do not have internal short circuit
protection circuitry. They have a typical short circuit current
of 80mA sourcing and 150mA sinking for the output is
connected to half way between the rails with a 10Ω resistor.
If the output is shorted indefinitely, the power dissipation
could easily increase such that the part will be destroyed.
Maximum reliability is maintained if the output current never
exceeds ±40mA. This limit is set by the design of the internal
metal interconnections.
Power Dissipation
With the high output drive capability of the EL8102, EL8103,
It is possible to exceed the +125°C absolute maximum
junction temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if the load
conditions or package types need to be modified for the
amplifier to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 2:
Where:
T
JMAX
= Maximum junction temperature
T
AMAX
= Maximum ambient temperature
θ
JA
= Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
For sourcing, Equation 3:
For sinking, Equation 4:
Where:
V
S
= Total supply voltage
I
SMAX
= Maximum quiescent supply current
V
OUT
= Maximum output voltage of the application
R
LOAD
= Load resistance tied to ground
I
LOAD
= Load current
By setting the two PD
MAX
equations equal to each other, we
can solve the output current and R
LOAD
to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the V
S
- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from V
S
+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier’s inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
PD
MAX
T
JMAX
T
AMAX
θ
JA
---------------------------------------------
=
(EQ. 2)
PD
MAX
V
S
I
SMAX
V
S
V
OUT
()
V
OUT
R
L
----------------
×+×= (EQ. 3)
PD
MAX
V
S
I
SMAX
V
OUT
V
S
-
()I
LOAD
×+×=
(EQ. 4)
EL8102, EL8103
11
FN7104.7
August 10, 2007
Typical Applications
VIDEO SYNC PULSE REMOVER
Many CMOS analog to digital converters have a parasitic
latch up problem when subjected to negative input voltage
levels. Since the sync tip contains no useful video
information and it is a negative going pulse, we can chop it
off. Figure 30 shows a gain of 2 connections for EL8102,
EL8103. Figure 31 shows the complete input video signal
applied at the input, as well as the output signal with the
negative going sync pulse removed.
MULTIPLEXER
Besides the normal power-down usage, the ENABLE
pin of
the EL8102 can be used for multiplexing applications. Figure
32 shows two EL8102 with the outputs tied together, driving
a back terminated 75Ω video load. A 2V
P-P
2MHz sine wave
is applied to Amp A and a 1V
P-P
2MHz sine wave is applied
to Amp B. Figure 33 shows the ENABLE
signal and the
resulting output waveform at V
OUT
. Observe the break-
before-make operation of the multiplexing. Amp A is on and
V
IN1
is passed through to the output when the ENABLE
signal is low and turns off in about 25ns when the ENABLE
signal is high. About 200ns later, Amp B turns on and V
IN2
is
passed through to the output. The break-before-make
operation ensures that more than one amplifier isn’t trying to
drive the bus at the same time.
SINGLE SUPPLY VIDEO LINE DRIVER
The EL8102 and EL8103 are wideband rail-to-rail output op
amplifiers with large output current, excellent dG, dP, and low
distortion that allow them to drive video signals in low supply
applications. Figure 34 is the single supply non-inverting
video line driver configuration and Figure 35 is the inverting
video line driver configuration. The signal is AC coupled by
C
1
. R
1
and R
2
are used to level shift the input and output to
provide the largest output swing. R
F
and R
G
set the AC gain.
C
2
isolates the virtual ground potential. R
T
and R
3
are the
termination resistors for the line. C
1
, C
2
and C
3
are selected
big enough to minimize the droop of the luminance signal.
FIGURE 30. SYNC PULSE REMOVER
5V
1k
V
OUT
V
IN
75Ω
+
-
75Ω
1k
75Ω
V
S+
V
S-
FIGURE 31. VIDEO SIGNAL
1V
0.5V
0V
1V
0.5V
0V
M = 10µs/DIV
V
OUT
V
IN
FIGURE 32. TWO TO ONE MULTIPLEXER
+2.5V
1k
2MHz
75Ω
+
-
1k
75Ω
-2.5V
V
OUT
75Ω
1V
P-P
B
+2.5V
1k
2MHz
+
-
1k
75Ω
-2.5V
2V
P-P
A
ENABLE
FIGURE 33.
0V
-0.5V
-1.5V
-2.5V
1V
0V
M = 50ns/DIV
A
ENABLE
B
-1V
EL8102, EL8103
12
FN7104.7
August 10, 2007
FIGURE 34. 5V SINGLE SUPPLY NON INVERTING
VIDEO LINE DRIVER
FIGURE 35. SINGLE SUPPLY INVERTING VIDEO LINE DRIVER
FIGURE 36. VIDEO LINE DRIVER FREQUENCY RESPONSE
5V
R
F
V
OUT
V
IN
75Ω
+
-
75Ω
1kΩ
75Ω
C
3
470µF
R
3
C
1
47µF
R
T
10k
10k
R
2
R
1
1kΩ
R
G
C
2
220µF
5V
R
F
V
OUT
V
IN
75Ω
-
+
75Ω
500Ω
75Ω
C
3
470µF
R
3
C
1
47µF
R
T
10k
10k
R
2
R
1
1kΩ
R
G
C
2
220µF
5V
4
3
2
1
0
-1
-2
-3
-4
-5
NORMALIZED GAIN (dB)
100K 1M 10M 100M 500M
FREQUENCY (Hz)
A
V
= -2
A
V
= 2
-6
EL8102, EL8103

EL8102IS-T13

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC OPAMP VFB 1 CIRCUIT 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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