LTC1701ES5#TRPBF

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LTC1701/LTC1701B
Input Capacitor (C
IN
) Selection
In continuous mode, the input current of the converter is
a square wave with a duty cycle of approximately V
OUT
/
V
IN
. To prevent large voltage transients, a low equivalent
series resistance (ESR) input capacitor sized for the maxi-
mum RMS current must be used. The maximum RMS
capacitor current is given by:
II
VVV
V
RMS MAX
OUT IN OUT
IN
()
where the maximum average output current I
MAX
equals
the peak current (1 Amp) minus half the peak-to-peak
ripple current, I
MAX
= 1 – I
L
/2.
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case is commonly used to
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours life-
time. This makes it advisable to further derate the capaci-
tor, or choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled to
meet the size or height requirements of the design. An
additional 0.1µF to 1µF ceramic capacitor is also recom-
mended on V
IN
for high frequency decoupling.
Output Capacitor (C
OUT
) Selection
The selection of C
OUT
is driven by the required ESR.
Typically, once the ESR requirement is satisfied, the
capacitance is adequate for filtering. The output ripple
(V
OUT
) is determined by:
∆≈ +
V I ESR
fC
OUT L
OUT
1
8
where f = operating frequency, C
OUT
= output capacitance
and I
L
= ripple current in the inductor. With I
L
= 0.4
I
OUT(MAX)
the output ripple will be less than 100mV with:
ESR
COUT
< 100m
Once the ESR requirements for C
OUT
have been met, the
RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement.
When the capacitance of C
OUT
is made too small, the
output ripple at low frequencies will be large enough to trip
the I
TH
comparator. This causes Burst Mode operation to
be activated when the LTC1701 would normally be in
continuous mode operation. The effect can be improved at
higher frequencies with lower inductor values.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Alumi-
num electrolyte and dry tantulum capacitors are both
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS, AVX TPSV and KEMET T510 series of
surface mount tantalums, avalable in case heights ranging
from 2mm to 4mm. Other capacitor types include Nichicon
PL series, Sanyo POSCAP and Panasonic SP.
Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempt-
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generates a loop “zero” at 5kHz to 50kHz that is instrumen-
tal in giving acceptable loop phase margin. Ceramic ca-
pacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
Also, ceramic caps are prone to temperature effects which
requires the designer to check loop stability over the
operating temperature range.
For these reasons, most of the input and output capaci-
tance should be composed of tantalum capacitors for
stability combined with about 0.1µF to 1µF of ceramic
capacitors for high frequency decoupling. Great care must
be taken when using only ceramic input and output capaci-
tors. The OPTI-LOOP compensation allows transient re-
sponse to be optimized for all types of output capacitors,
including low ESR ceramics.
Setting the Output Voltage
The LTC1701 develops a 1.25V reference voltage between
the feedback pin, V
FB
, and the signal ground as shown in
APPLICATIO S I FOR ATIO
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LTC1701/LTC1701B
Figure 2. The output voltage is set by a resistive divider
according to the following formula:
V
OUT
= 1.25V(1 + R2/R1)
To prevent stray pickup, a capacitor of about 5pF can be
added across R1, located close to the LTC1701. Unfortu-
nately, the load step response is degraded by this capaci-
tor. Using a good printed circuit board layout eliminates
the need for this capacitor. Great care should be taken to
route the V
FB
line away from noise sources, such as the
inductor or the SW line.
APPLICATIO S I FOR ATIO
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V
FB
SGND
LTC1701
R2
1%
R1
1%
1701 F02
V
OUT
C
F
5pF
Transient Response
The OPTI-LOOP compensation allows the transient re-
sponse to be optimized for a wide range of loads and
output capacitors. The availability of the I
TH
pin not only
allows optimization of the control loop behavior but also
provides a DC coupled and AC filtered closed-loop re-
sponse test point. The DC step, rise time and settling at this
test point truly reflects the closed-loop response. Assum-
ing a predominately second order system, phase margin
and/or damping factor can be estimated using the percent-
age of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin.
The I
TH
external components shown in the Figure 1 circuit
will provide an adequate starting point for most applica-
tions. The series R3-C3 filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phrase. An output current pulse
Figure 2. Setting the Output Voltage
of 20% to 100% of full-load current having a rise time of
1µs to 10µs will produce output voltage and I
TH
pin
waveforms that will give a sense of the overall loop
stability without breaking the feedback loop.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second-
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R3 and
the bandwidth of the loop increases with decreasing C3. If
R3 is increased by the same factor that C3 is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range of
the feedback loop. In addition, a feed-forward capacitor,
C
F
, can be added to improve the high frequency response,
as shown in Figure 2. Capacitor C
F
provides phase lead by
creating a high frequency zero with R2 which improves the
phase margin.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Applica-
tion Note 76.
RUN Function
The I
TH
/RUN pin is a dual purpose pin that provides the
loop compensation and a means to shut down the LTC1701.
Soft-start can also be implemented with this pin. Soft-start
reduces surge currents from V
IN
by gradually increasing
the internal peak inductor current. Power supply sequenc-
ing can also be accomplished using this pin.
An external pull-up is required to charge the external
capacitor C3 in Figure 1. Typically, a 1M resistor between
V
IN
and I
TH
/RUN is used. When the voltage on I
TH
/RUN
reaches about 0.8V the LTC1701 begins operating. At this
point the error amplifier pulls up the I
TH
/RUN pin to the
normal operating range of 1.25V to 2.25V.
Soft-start can be implemented by ramping the voltage on
I
TH
/RUN during start-up as shown in Figure 3(b). As the
voltage on I
TH
/RUN ramps through its operating range the
internal peak current limit is also ramped at a proportional
linear rate.
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LTC1701/LTC1701B
APPLICATIO S I FOR ATIO
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During normal operation the voltage on the I
TH
/RUN pin
will vary from 1.25V to 2.25V depending on the load
current. Pulling the I
TH
/RUN pin below 0.8V puts the
LTC1701 into a low quiescent current shutdown mode
(I
Q
< 1µA). This pin can be driven directly from logic as
shown in Figures 3(a).
continuous mode, I
GATECHG
= f • Q
P
, where Q
P
is the gate
charge of the internal MOSFET switch.
3) I
2
R Losses are predicted from the DC resistances of the
MOSFET and inductor. In continuous mode the average
output current flows through L, but is “chopped” between
the topside internal MOSFET and the Schottky diode. At
low supply voltages where the switch on-resistance is
higher and the switch is on for longer periods due to the
higher duty cycle, the switch losses will dominate. Using
a larger inductance helps minimize these switch losses. At
high supply voltages, these losses are proportional to the
load. I
2
R losses cause the efficiency to drop at high output
currents.
4) The Schottky diode is a major source of power loss at
high currents and gets worse at low output voltages. The
diode loss is calculated by multiplying the forward voltage
drop times the diode duty cycle multiplied by the load
current.
Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C
IN
has adequate
charge storage and very low ESR at the switching fre-
quency. Other losses including Schottky conduction losses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.
THERMAL CONSIDERATIONS
The power handling capability of the device at high ambi-
ent temperatures will be limited by the maximum rated
junction temperature (125°C). It is important to give
careful consideration to all sources of thermal resistance
from junction to ambient. Additional heat sources mounted
nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
Figure 3. I
TH
/RUN Pin Interfacing
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and what change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC1701 circuits: 1) LTC1701 V
IN
current,
2)␣ switching losses, 3) I
2
R losses, 4) Schottky diode
losses.
1) The V
IN
current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. V
IN
current results in a small (< 0.1%)
loss that increases with V
IN
, even at no load.
2) The switching current is the sum of the internal MOSFET
driver and control currents. The MOSFET driver current
results from switching the gate capacitance of the power
MOSFET. Each time a MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves from V
IN
to ground. The resulting dQ/dt is a current out of V
IN
that
is typically much larger than the control circuit current. In
D1
I
TH
/RUN
C
C
R
C
1701 F03
I
TH
/RUN
C
C
R
C
C1
R1
(a)
(b)

LTC1701ES5#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1MHz Buck DC/DC Conv in SOT-23
Lifecycle:
New from this manufacturer.
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